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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "ARM: dts: msm: Adding IPA nodes for yupik target"
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148
qcom/yupik.dtsi
148
qcom/yupik.dtsi
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@ -2318,6 +2318,18 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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/* ipa - inbound entry from mss */
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smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
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qcom,entry-name = "ipa";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-wpss {
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@ -3525,6 +3537,142 @@
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dma-coherent-hint-cached;
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};
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};
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qcom,msm_gsi {
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compatible = "qcom,msm_gsi";
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};
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qcom,rmnet-ipa {
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compatible = "qcom,rmnet-ipa3";
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qcom,rmnet-ipa-ssr;
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qcom,ipa-platform-type-msm;
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qcom,ipa-advertise-sg-support;
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qcom,ipa-napi-enable;
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};
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qcom,ipa_fws {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <0xf>;
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qcom,firmware-name = "yupik_ipa_fws";
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qcom,pil-force-shutdown;
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memory-region = <&pil_ipa_gsi_mem>;
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};
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ipa_hw: qcom,ipa@1e00000 {
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compatible = "qcom,ipa";
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mboxes = <&qmp_aop 0>;
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reg =
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<0x1e00000 0x84000>,
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<0x1e04000 0x23000>;
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reg-names = "ipa-base", "gsi-base";
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interrupts =
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<0 654 IRQ_TYPE_LEVEL_HIGH>,
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<0 432 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ipa-irq", "gsi-irq";
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qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */
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qcom,ipa-hw-mode = <0>;
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qcom,platform-type = <1>; /* MSM platform */
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qcom,ee = <0>;
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qcom,use-ipa-tethering-bridge;
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qcom,modem-cfg-emb-pipe-flt;
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qcom,ipa-wdi3-over-gsi;
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qcom,arm-smmu;
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qcom,smmu-fast-map;
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qcom,use-64-bit-dma-mask;
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qcom,ipa-endp-delay-wa-v2;
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qcom,lan-rx-napi;
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qcom,tx-napi;
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qcom,wan-use-skb-page;
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qcom,rmnet-ctl-enable;
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qcom,ipa-uc-holb-monitor;
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qcom,use-gsi-ipa-fw = "yupik_ipa_fws";
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qcom,gsi_wdi_db_polling;
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qcom,ipa-holb-monitor-poll-period = <5>;
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qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
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qcom,ipa-holb-monitor-max-cnt-usb = <10>;
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qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
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qcom,tx-wrapper-cache-max-size = <400>;
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qcom,ipa-gpi-event-rp-ddr;
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clock-names = "core_clk";
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clocks = <&rpmhcc RPMH_IPA_CLK>;
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qcom,interconnect,num-cases = <5>;
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qcom,interconnect,num-paths = <3>;
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interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
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<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>;
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interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
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/* No vote */
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qcom,no-vote =
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<0 0 0 0 0 0>;
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/* SVS2 */
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qcom,svs2 =
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<150000 600000 150000 1804000 0 74000>;
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/* SVS */
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qcom,svs =
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<625000 1200000 625000 3072000 0 150000>;
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/* NOMINAL */
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qcom,nominal =
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<1250000 2400000 1250000 6220800 0 400000>;
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/* TURBO */
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qcom,turbo =
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<2000000 3500000 2000000 7219200 0 400000>;
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qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
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"TURBO";
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qcom,throughput-threshold = <600 2500 5000>;
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qcom,scaling-exceptions = <>;
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/* smp2p information */
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qcom,smp2p_map_ipa_1_out {
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compatible = "qcom,smp2p-map-ipa-1-out";
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qcom,smem-states = <&smp2p_ipa_1_out 0>;
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qcom,smem-state-names = "ipa-smp2p-out";
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};
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qcom,smp2p_map_ipa_1_in {
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compatible = "qcom,smp2p-map-ipa-1-in";
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interrupts-extended = <&smp2p_ipa_1_in 0 0>;
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interrupt-names = "ipa-smp2p-in";
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};
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ipa_smmu_ap: ipa_smmu_ap {
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compatible = "qcom,ipa-smmu-ap-cb";
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iommus = <&apps_smmu 0x480 0x0>;
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qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
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qcom,additional-mapping =
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/* modem tables in IMEM */
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<0x146A8000 0x146A8000 0x2000>;
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dma-coherent;
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qcom,iommu-dma = "fastmap";
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qcom,ipa-q6-smem-size = <36864>;
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};
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ipa_smmu_wlan: ipa_smmu_wlan {
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compatible = "qcom,ipa-smmu-wlan-cb";
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iommus = <&apps_smmu 0x481 0x0>;
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qcom,iommu-dma = "atomic";
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dma-coherent;
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};
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ipa_smmu_uc: ipa_smmu_uc {
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compatible = "qcom,ipa-smmu-uc-cb";
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iommus = <&apps_smmu 0x482 0x0>;
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qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
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qcom,iommu-dma = "atomic";
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};
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ipa_smmu_11ad: ipa_smmu_11ad {
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compatible = "qcom,ipa-smmu-11ad-cb";
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iommus = <&apps_smmu 0x483 0x0>;
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dma-coherent;
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qcom,shared-cb;
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qcom,iommu-group = <>;
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};
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};
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};
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#include "shima-gdsc.dtsi"
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