mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 08:07:32 -04:00
Merge "ARM: dts: msm: Enable device nodes for PIL on SM6150"
This commit is contained in:
qctecmdr
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commit
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4 changed files with 382 additions and 0 deletions
249
qcom/msm-arm-smmu-sm6150.dtsi
Normal file
249
qcom/msm-arm-smmu-sm6150.dtsi
Normal file
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@ -0,0 +1,249 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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kgsl_smmu: kgsl-smmu@0x50a0000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x50a0000 0x10000>,
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<0x50c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,dynamic;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cx_gdsc>;
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gpu_cc_ahb_clk",
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"gpu_cc_hlos1_vote_gpu_smmu_clk";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
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gfx_0_tbu: gfx_0_tbu@0x50c5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x50c5000 0x1000>,
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<0x50c2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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};
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gfx_1_tbu: gfx_1_tbu@0x50c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x50c9000 0x1000>,
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<0x50c2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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};
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};
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apps_smmu: apps-smmu@0x15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x80000>,
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<0x150c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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anoc_1_tbu: anoc_1_tbu@0x150c5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150c5000 0x1000>,
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<0x150c2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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anoc_2_tbu: anoc_2_tbu@0x150c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150c9000 0x1000>,
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<0x150c2208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150cd000 0x1000>,
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<0x150c2210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_MDP0
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&mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
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};
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mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d1000 0x1000>,
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<0x150c2218 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
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qcom,active-only;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
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};
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compute_dsp_tbu: compute_dsp_tbu@0x150d5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d5000 0x1000>,
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<0x150c2220 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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/* No GDSC */
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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adsp_tbu: adsp_tbu@0x150d9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x150d9000 0x1000>,
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<0x150c2228 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
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qcom,active-only;
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interconnects = <&system_noc MASTER_GEM_NOC_SNOC
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&config_noc SLAVE_IMEM_CFG>;
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};
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};
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kgsl_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x7 0>;
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};
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kgsl_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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iommus = <&kgsl_smmu 0x9 0>;
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dma-coherent;
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};
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apps_iommu_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x21 0>;
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};
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apps_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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iommus = <&apps_smmu 0x23 0>;
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dma-coherent;
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};
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};
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&kgsl_smmu {
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qcom,actlr =
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/* All CBs of GFX: +15 deep PF */
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<0x0 0x7ff 0x303>;
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};
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&apps_smmu {
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qcom,actlr =
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/* HF and SF TBUs: +3 deep PF */
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<0x800 0x7ff 0x103>;
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};
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@ -3,3 +3,17 @@
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&qupv3_0 {
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status = "ok"
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};
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&soc {
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qcom,lpass@62400000 {
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status = "ok"
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};
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qcom,venus@aae0000 {
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status = "ok"
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};
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qcom,turing@8300000 {
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status = "ok"
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};
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};
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@ -39,5 +39,11 @@
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/delete-node/ rpmh-regulator-bobc1;
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};
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&soc {
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qcom,lpass@62400000 {
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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};
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};
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#include "sa6155-regulator.dtsi"
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#include "pm6155.dtsi"
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|
|
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113
qcom/sm6150.dtsi
113
qcom/sm6150.dtsi
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@ -12,6 +12,7 @@
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sm6150.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/ {
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model = "Qualcomm Technologies, Inc. SM6150";
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@ -1560,6 +1561,116 @@
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#interrupt-cells = <2>;
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};
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};
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qcom,lpass@62400000 {
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compatible = "qcom,pil-tz-generic";
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reg = <0x62400000 0x00100>;
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vdd_cx-supply = <&L8A_LEVEL>;
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
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qcom,proxy-reg-names = "vdd_cx";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
|
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clock-names = "xo";
|
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qcom,proxy-clock-names = "xo";
|
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|
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qcom,pas-id = <1>;
|
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qcom,proxy-timeout-ms = <10000>;
|
||||
qcom,smem-id = <423>;
|
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qcom,sysmon-id = <1>;
|
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qcom,ssctl-instance-id = <0x14>;
|
||||
qcom,firmware-name = "adsp";
|
||||
memory-region = <&pil_adsp_mem>;
|
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qcom,signal-aop;
|
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qcom,complete-ramdump;
|
||||
|
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/* Inputs from lpass */
|
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interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
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<&adsp_smp2p_in 0 0>,
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<&adsp_smp2p_in 2 0>,
|
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<&adsp_smp2p_in 1 0>,
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<&adsp_smp2p_in 3 0>,
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<&adsp_smp2p_in 7 0>;
|
||||
interrupt-names = "qcom,wdog",
|
||||
"qcom,err-fatal",
|
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"qcom,proxy-unvote",
|
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"qcom,err-ready",
|
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"qcom,stop-ack",
|
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"qcom,shutdown-ack";
|
||||
|
||||
/* Outputs to lpass */
|
||||
qcom,smem-states = <&adsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "qcom,force-stop";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "adsp-pil";
|
||||
};
|
||||
qcom,turing@8300000 {
|
||||
compatible = "qcom,pil-tz-generic";
|
||||
reg = <0x8300000 0x100000>;
|
||||
|
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vdd_cx-supply = <&VDD_CX_LEVEL>;
|
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qcom,proxy-reg-names = "vdd_cx";
|
||||
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
qcom,proxy-clock-names = "xo";
|
||||
|
||||
qcom,pas-id = <18>;
|
||||
qcom,proxy-timeout-ms = <10000>;
|
||||
qcom,smem-id = <601>;
|
||||
qcom,sysmon-id = <7>;
|
||||
qcom,ssctl-instance-id = <0x17>;
|
||||
qcom,firmware-name = "cdsp";
|
||||
memory-region = <&pil_cdsp_mem>;
|
||||
qcom,signal-aop;
|
||||
qcom,complete-ramdump;
|
||||
|
||||
/* Inputs from turing */
|
||||
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&cdsp_smp2p_in 0 0>,
|
||||
<&cdsp_smp2p_in 2 0>,
|
||||
<&cdsp_smp2p_in 1 0>,
|
||||
<&cdsp_smp2p_in 3 0>,
|
||||
<&cdsp_smp2p_in 7 0>;
|
||||
|
||||
interrupt-names = "qcom,wdog",
|
||||
"qcom,err-fatal",
|
||||
"qcom,proxy-unvote",
|
||||
"qcom,err-ready",
|
||||
"qcom,stop-ack",
|
||||
"qcom,shutdown-ack";
|
||||
|
||||
/* Outputs to turing */
|
||||
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "qcom,force-stop";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "cdsp-pil";
|
||||
};
|
||||
|
||||
qcom,venus@aae0000 {
|
||||
compatible = "qcom,pil-tz-generic";
|
||||
reg = <0xaae0000 0x4000>;
|
||||
|
||||
vdd-supply = <&venus_gdsc>;
|
||||
qcom,proxy-reg-names = "vdd";
|
||||
|
||||
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
|
||||
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
|
||||
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_clk";
|
||||
qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
|
||||
|
||||
qcom,pas-id = <9>;
|
||||
interconnect-names = "pil-venus";
|
||||
interconnects = <&mmss_noc MASTER_VIDEO_P0
|
||||
&mc_virt SLAVE_EBI1>;
|
||||
qcom,proxy-timeout-ms = <100>;
|
||||
qcom,firmware-name = "venus";
|
||||
memory-region = <&pil_video_mem>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "sm6150-qupv3.dtsi"
|
||||
|
|
@ -1663,3 +1774,5 @@
|
|||
&venus_gdsc {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
#include "msm-arm-smmu-sm6150.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue