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dt-bindings: clock: add support for DSI CPHY clocks

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Add CPHY specific clocks to support MIPI DSI CPHY on
Lahaina hardware. Add the relevant clock bindings.

Change-Id: If7dd806e6427b65427d5999bb9ccda7098ec610b
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
This commit is contained in:
Yuan Zhao 2020-05-08 11:55:18 +08:00
commit 7def97e0a3
1 changed files with 29 additions and 18 deletions
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47
include/dt-bindings/clock/mdss-5nm-pll-clk.h
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@ -25,24 +25,35 @@
#define SHADOW_POST_VCO_DIV_0_CLK 15
#define SHADOW_PCLK_SRC_MUX_0_CLK 16
#define SHADOW_PCLK_SRC_0_CLK 17
#define VCO_CLK_1 18
#define PLL_OUT_DIV_1_CLK 19
#define BITCLK_SRC_1_CLK 20
#define BYTECLK_SRC_1_CLK 21
#define POST_BIT_DIV_1_CLK 22
#define POST_VCO_DIV_1_CLK 23
#define BYTECLK_MUX_1_CLK 24
#define PCLK_SRC_MUX_1_CLK 25
#define PCLK_SRC_1_CLK 26
#define PCLK_MUX_1_CLK 27
#define SHADOW_VCO_CLK_1 28
#define SHADOW_PLL_OUT_DIV_1_CLK 29
#define SHADOW_BITCLK_SRC_1_CLK 30
#define SHADOW_BYTECLK_SRC_1_CLK 31
#define SHADOW_POST_BIT_DIV_1_CLK 32
#define SHADOW_POST_VCO_DIV_1_CLK 33
#define SHADOW_PCLK_SRC_MUX_1_CLK 34
#define SHADOW_PCLK_SRC_1_CLK 35
/* CPHY clocks for DSI-0 PLL */
#define CPHY_BYTECLK_SRC_0_CLK 18
#define POST_VCO_DIV3_5_0_CLK 19
#define CPHY_PCLK_SRC_MUX_0_CLK 20
#define CPHY_PCLK_SRC_0_CLK 21
#define VCO_CLK_1 22
#define PLL_OUT_DIV_1_CLK 23
#define BITCLK_SRC_1_CLK 24
#define BYTECLK_SRC_1_CLK 25
#define POST_BIT_DIV_1_CLK 26
#define POST_VCO_DIV_1_CLK 27
#define BYTECLK_MUX_1_CLK 28
#define PCLK_SRC_MUX_1_CLK 29
#define PCLK_SRC_1_CLK 30
#define PCLK_MUX_1_CLK 31
#define SHADOW_VCO_CLK_1 32
#define SHADOW_PLL_OUT_DIV_1_CLK 33
#define SHADOW_BITCLK_SRC_1_CLK 34
#define SHADOW_BYTECLK_SRC_1_CLK 35
#define SHADOW_POST_BIT_DIV_1_CLK 36
#define SHADOW_POST_VCO_DIV_1_CLK 37
#define SHADOW_PCLK_SRC_MUX_1_CLK 38
#define SHADOW_PCLK_SRC_1_CLK 39
/* CPHY clocks for DSI-1 PLL */
#define CPHY_BYTECLK_SRC_1_CLK 40
#define POST_VCO_DIV3_5_1_CLK 41
#define CPHY_PCLK_SRC_MUX_1_CLK 42
#define CPHY_PCLK_SRC_1_CLK 43
/* DP PLL clocks */
#define DP_VCO_CLK 0