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ARM: dts: msm: add PCIe pipe clk mux and ext src to PCIe clock for lahaina

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PCIe needs to switch between XO and pcie_*_pipe_clk based on
LPM state. Add the clocks to support this on lahaina.

Change-Id: I44efe4752d5a9d93a7fff5809b272fa4b6146f14
This commit is contained in:
Tony Truong 2020-01-30 12:53:30 -08:00 • committed by Gerrit - the friendly Code Review server
commit 7f4bcfef39
1 changed files with 12 additions and 6 deletions
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18
qcom/lahaina-pcie.dtsi
View file

@ -70,7 +70,9 @@
<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&clock_gcc PCIE_0_PIPE_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
@ -78,10 +80,11 @@
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk",
"pcie_aggre_noc_1_axi_clk";
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>;
<0>, <0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_0_BCR>,
<&clock_gcc GCC_PCIE_0_PHY_BCR>;
@ -221,17 +224,20 @@
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&clock_gcc PCIE_1_PIPE_CLK>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_1_axi_clk";
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>;
<0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_1_BCR>,
<&clock_gcc GCC_PCIE_1_PHY_BCR>;