mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 23:24:22 -04:00
Merge "ARM: dts: msm: Base device tree of SA6155 GVM"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
80abbe71b7
6 changed files with 1036 additions and 1 deletions
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@ -346,7 +346,8 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \
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sa8195-vm-lv.dtb \
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sa8195-vm-la-mt.dtb \
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sa8195-vm-lv-mt.dtb \
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sa8195-vm-lv-lxc.dtb
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sa8195-vm-lv-lxc.dtb \
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sa6155p-vm-la.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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11
qcom/sa6155p-vm-la.dts
Normal file
11
qcom/sa6155p-vm-la.dts
Normal file
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sa6155p-vm.dtsi"
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#include "sa6155p-vm-la.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine";
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compatible = "qcom,sa6155p";
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qcom,pmic-name = "PM6150";
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qcom,board-id = <0x1000001 0>;
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};
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35
qcom/sa6155p-vm-la.dtsi
Normal file
35
qcom/sa6155p-vm-la.dtsi
Normal file
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@ -0,0 +1,35 @@
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&reserved_memory {
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pmem_shared: pmem_shared_region@a1600000 {
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reg = <0x0 0xa1600000 0x0 0x20000000>;
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label = "pmem_shared_mem";
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};
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};
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/ {
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rename_blk: rename_blk {
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compatible = "qcom,blkdev-rename";
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actual-dev = "vda", "vdb", "vdc",
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"vdd", "vde", "vdf",
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"vdg", "vdh";
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rename-dev = "system", "userdata", "vendor",
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"persist", "modem", "bluetooth",
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"misc", "vbmeta";
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};
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};
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&usb0 {
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status = "ok"
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};
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&qusb_phy0 {
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status = "ok"
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};
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&pcie0_msi {
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status = "ok"
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};
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&pcie0 {
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status = "ok"
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};
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249
qcom/sa6155p-vm-pcie.dtsi
Normal file
249
qcom/sa6155p-vm-pcie.dtsi
Normal file
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@ -0,0 +1,249 @@
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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&soc {
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pcie0: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c08000 0x4000>,
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<0x1c0e000 0x1000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x40200000 0x100000>,
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<0x40300000 0x1fd00000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "io", "bars";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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qcom,phy-sequence = <0x0800 0x01 0x0
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0x0804 0x03 0x0
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0x0034 0x18 0x0
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0x0038 0x10 0x0
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0x0070 0x0f 0x0
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0x00c8 0x01 0x0
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0x0128 0x00 0x0
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0x0144 0xff 0x0
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0x0148 0x1f 0x0
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0x0194 0x06 0x0
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0x0048 0x0f 0x0
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0x0178 0x00 0x0
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0x019c 0x01 0x0
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0x018c 0x20 0x0
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0x0184 0x0a 0x0
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0x00b4 0x20 0x0
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0x000c 0x09 0x0
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0x00ac 0x04 0x0
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0x00d0 0x82 0x0
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0x00e4 0x03 0x0
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0x00e0 0x55 0x0
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0x00dc 0x55 0x0
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0x0054 0x00 0x0
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0x0050 0x0d 0x0
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0x004c 0x04 0x0
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0x0174 0x35 0x0
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0x003c 0x02 0x0
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0x0040 0x1f 0x0
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0x0078 0x04 0x0
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0x0084 0x16 0x0
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0x0090 0x30 0x0
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0x010c 0x00 0x0
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0x0108 0x80 0x0
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0x00a8 0x01 0x0
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0x000c 0x0a 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0014 0x02 0x0
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0x0018 0x00 0x0
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0x0024 0x2f 0x0
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0x0028 0x19 0x0
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0x0268 0x45 0x0
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0x0194 0x06 0x0
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0x024c 0x02 0x0
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0x02ac 0x12 0x0
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0x0510 0x1c 0x0
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0x051c 0x14 0x0
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0x04d8 0x01 0x0
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0x04dc 0x00 0x0
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0x04e0 0xdb 0x0
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0x0448 0x4b 0x0
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0x041c 0x04 0x0
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0x0410 0x04 0x0
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0x0074 0x19 0x0
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0x0854 0x04 0x0
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0x09ac 0x00 0x0
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0x08a0 0x40 0x0
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0x09e0 0x00 0x0
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0x09dc 0x40 0x0
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0x09a8 0x00 0x0
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0x08a4 0x40 0x0
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0x08a8 0x73 0x0
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0x09b0 0x07 0x0
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0x09d8 0x99 0x0
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0x0824 0x15 0x0
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0x0828 0x0e 0x0
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0x0800 0x00 0x0
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0x0808 0x03 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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perst-gpio = <&tlmm 101 0>;
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wake-gpio = <&tlmm 100 0>;
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gdsc-vdd-supply = <&pcie_0_gdsc>;
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vreg-1p8-supply = <&L12A>;
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vreg-0p9-supply = <&L5A>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1800000 1800000 24000>;
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qcom,vreg-0p9-voltage-level = <925000 925000 24000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_NOM 100000000>;
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qcom,no-l0s-supported;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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msi-parent = <&pcie0_msi>;
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qcom,max-link-speed = <0x2>;
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qcom,ep-latency = <10>;
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qcom,slv-addr-space-size = <0x20000000>;
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qcom,phy-status-offset = <0x974>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x804>;
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qcom,core-preset = <0x77777777>;
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qcom,boot-option = <0x1>;
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linux,pci-domain = <0>;
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qcom,pcie-phy-ver = <2609>;
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qcom,use-19p2mhz-aux-clk;
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qcom,smmu-sid-base = <0x0400>;
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iommu-map = <0x0 &apps_smmu 0x0400 0x1>,
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<0x100 &apps_smmu 0x0401 0x1>,
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<0x200 &apps_smmu 0x0402 0x1>,
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<0x300 &apps_smmu 0x0403 0x1>,
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<0x400 &apps_smmu 0x0404 0x1>,
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<0x500 &apps_smmu 0x0405 0x1>,
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<0x600 &apps_smmu 0x0406 0x1>,
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<0x700 &apps_smmu 0x0407 0x1>,
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<0x800 &apps_smmu 0x0408 0x1>,
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<0x900 &apps_smmu 0x0409 0x1>,
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<0xa00 &apps_smmu 0x040a 0x1>,
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<0xb00 &apps_smmu 0x040b 0x1>,
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<0xc00 &apps_smmu 0x040c 0x1>,
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<0xd00 &apps_smmu 0x040d 0x1>,
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<0xe00 &apps_smmu 0x040e 0x1>,
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<0xf00 &apps_smmu 0x040f 0x1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_PHY_AUX_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk", "pcie_phy_aux_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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status = "disabled";
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pcie_rc0: pcie_rc0 {
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#address-cells = <5>;
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#size-cells = <0>;
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:010a";
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a00040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a00040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 672 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 673 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 674 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 675 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 676 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
|
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<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 683 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 684 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 685 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 686 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 687 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 689 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 690 IRQ_TYPE_EDGE_RISING>,
|
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<GIC_SPI 691 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 692 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 693 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 694 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 695 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 696 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 697 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 701 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
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||||
|
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status = "disabled";
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||||
};
|
||||
};
|
||||
412
qcom/sa6155p-vm-usb.dtsi
Normal file
412
qcom/sa6155p-vm-usb.dtsi
Normal file
|
|
@ -0,0 +1,412 @@
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|||
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
|
||||
|
||||
&soc {
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||||
/* Primary USB port related controller */
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||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa600000 0x100000>;
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||||
reg-names = "core_base";
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||||
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
|
||||
#address-cells = <1>;
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||||
#size-cells = <1>;
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||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
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||||
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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||||
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"ss_phy_irq", "dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
||||
dpdm-supply = <&qusb_phy0>;
|
||||
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"xo", "sleep_clk", "utmi_clk";
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,num-gsi-evt-buffs = <0x3>;
|
||||
qcom,gsi-reg-offset =
|
||||
<0x0fc /* GSI_GENERAL_CFG */
|
||||
0x110 /* GSI_DBL_ADDR_L */
|
||||
0x120 /* GSI_DBL_ADDR_H */
|
||||
0x130 /* GSI_RING_BASE_ADDR_L */
|
||||
0x144 /* GSI_RING_BASE_ADDR_H */
|
||||
0x1a4>; /* GSI_IF_STS */
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
|
||||
qcom,pm-qos-latency = <61>;
|
||||
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
|
||||
|
||||
dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa600000 0xcd00>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&qusb_phy0>, <&usb_nop_phy>;
|
||||
tx-fifo-resize;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
snps,usb3_lpm_capable;
|
||||
usb-core-id = <0>;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
usbbam: qcom,usbbam@a704000 {
|
||||
compatible = "qcom,usb-bam-msm";
|
||||
reg = <0xa704000 0x17000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
|
||||
qcom,usb-bam-num-pipes = <4>;
|
||||
qcom,disable-clk-gating;
|
||||
qcom,usb-bam-override-threshold = <0x4001>;
|
||||
qcom,usb-bam-max-mbps-highspeed = <400>;
|
||||
qcom,usb-bam-max-mbps-superspeed = <3600>;
|
||||
qcom,reset-bam-on-connect;
|
||||
status = "disabled";
|
||||
qcom,pipe0 {
|
||||
label = "ssusb-qdss-in-0";
|
||||
qcom,usb-bam-mem-type = <2>;
|
||||
qcom,dir = <1>;
|
||||
qcom,pipe-num = <0>;
|
||||
qcom,peer-bam = <0>;
|
||||
qcom,peer-bam-physical-address = <0x6064000>;
|
||||
qcom,src-bam-pipe-index = <0>;
|
||||
qcom,dst-bam-pipe-index = <0>;
|
||||
qcom,data-fifo-offset = <0x0>;
|
||||
qcom,data-fifo-size = <0x1800>;
|
||||
qcom,descriptor-fifo-offset = <0x1800>;
|
||||
qcom,descriptor-fifo-size = <0x800>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary USB port related High Speed PHY */
|
||||
qusb_phy0: qusb@88e2000 {
|
||||
compatible = "qcom,qusb2phy";
|
||||
reg = <0x88e2000 0x180>,
|
||||
<0x01fcb250 0x4>,
|
||||
<0x007801f8 0x4>,
|
||||
<0x01fcb3e4 0x4>;
|
||||
reg-names = "qusb_phy_base",
|
||||
"tcsr_clamp_dig_n_1p8",
|
||||
"tune2_efuse_addr",
|
||||
"tcsr_conn_box_spare_0";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L13A>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,tune2-efuse-bit-pos = <25>;
|
||||
qcom,tune2-efuse-num-bits = <4>;
|
||||
qcom,qusb-phy-init-seq = <0xc8 0x80
|
||||
0xb3 0x84
|
||||
0x83 0x88
|
||||
0xc0 0x8c
|
||||
0x30 0x08
|
||||
0x79 0x0c
|
||||
0x21 0x10
|
||||
0x14 0x9c
|
||||
0x9f 0x1c
|
||||
0x00 0x18>;
|
||||
phy_type = "utmi";
|
||||
qcom,phy-clk-scheme = "cml";
|
||||
qcom,major-rev = <1>;
|
||||
|
||||
/* USB2PHY gets clock directly from CXO pad
|
||||
* connected to differential pin cxo_core_in_1p8_vdda.
|
||||
*/
|
||||
clocks = <&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
clock-names = "ref_clk_src", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Primary USB port related QMP USB PHY */
|
||||
usb_qmp_phy: ssphy@88e6000 {
|
||||
compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
|
||||
reg = <0x88e6000 0x1000>,
|
||||
<0x01fcb244 0x4>;
|
||||
reg-names = "qmp_phy_base",
|
||||
"vls_clamp_reg";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
core-supply = <&L12A>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,core-voltage-level = <0 1800000 1800000>;
|
||||
qcom,qmp-phy-init-seq =
|
||||
/* <reg_offset, value, delay> */
|
||||
<0xac 0x14 0x00
|
||||
0x34 0x08 0x00
|
||||
0x174 0x30 0x00
|
||||
0x3c 0x06 0x00
|
||||
0xb4 0x00 0x00
|
||||
0xb8 0x08 0x00
|
||||
0x70 0x0f 0x00
|
||||
0x19c 0x01 0x00
|
||||
0x178 0x00 0x00
|
||||
0xd0 0x82 0x00
|
||||
0xdc 0x55 0x00
|
||||
0xe0 0x55 0x00
|
||||
0xe4 0x03 0x00
|
||||
0x78 0x0b 0x00
|
||||
0x84 0x16 0x00
|
||||
0x90 0x28 0x00
|
||||
0x108 0x80 0x00
|
||||
0x10c 0x00 0x00
|
||||
0x184 0x0a 0x00
|
||||
0x4c 0x15 0x00
|
||||
0x50 0x34 0x00
|
||||
0x54 0x00 0x00
|
||||
0xc8 0x00 0x00
|
||||
0x18c 0x00 0x00
|
||||
0xcc 0x00 0x00
|
||||
0x128 0x00 0x00
|
||||
0x0c 0x0a 0x00
|
||||
0x10 0x01 0x00
|
||||
0x1c 0x31 0x00
|
||||
0x20 0x01 0x00
|
||||
0x14 0x00 0x00
|
||||
0x18 0x00 0x00
|
||||
0x24 0xde 0x00
|
||||
0x28 0x07 0x00
|
||||
0x48 0x0f 0x00
|
||||
0x194 0x06 0x00
|
||||
0x100 0x80 0x00
|
||||
0xa8 0x01 0x00
|
||||
0x430 0x0b 0x00
|
||||
0x830 0x0b 0x00
|
||||
0x444 0x00 0x00
|
||||
0x844 0x00 0x00
|
||||
0x43c 0x00 0x00
|
||||
0x83c 0x00 0x00
|
||||
0x440 0x00 0x00
|
||||
0x840 0x00 0x00
|
||||
0x408 0x0a 0x00
|
||||
0x808 0x0a 0x00
|
||||
0x414 0x06 0x00
|
||||
0x814 0x06 0x00
|
||||
0x434 0x75 0x00
|
||||
0x834 0x75 0x00
|
||||
0x4d4 0x02 0x00
|
||||
0x8d4 0x02 0x00
|
||||
0x4d8 0x4e 0x00
|
||||
0x8d8 0x4e 0x00
|
||||
0x4dc 0x18 0x00
|
||||
0x8dc 0x18 0x00
|
||||
0x4f8 0x77 0x00
|
||||
0x8f8 0x77 0x00
|
||||
0x4fc 0x80 0x00
|
||||
0x8fc 0x80 0x00
|
||||
0x4c0 0x0a 0x00
|
||||
0x8c0 0x0a 0x00
|
||||
0x504 0x03 0x00
|
||||
0x904 0x03 0x00
|
||||
0x50c 0x16 0x00
|
||||
0x90c 0x16 0x00
|
||||
0x500 0x00 0x00
|
||||
0x900 0x00 0x00
|
||||
0x564 0x00 0x00
|
||||
0x964 0x00 0x00
|
||||
0x260 0x10 0x00
|
||||
0x660 0x10 0x00
|
||||
0x2a4 0x12 0x00
|
||||
0x6a4 0x12 0x00
|
||||
0x28c 0xc6 0x00
|
||||
0x68c 0xc6 0x00
|
||||
0x244 0x00 0x00
|
||||
0x644 0x00 0x00
|
||||
0x248 0x00 0x00
|
||||
0x648 0x00 0x00
|
||||
0xc0c 0x9f 0x00
|
||||
0xc24 0x17 0x00
|
||||
0xc28 0x0f 0x00
|
||||
0xcc8 0x83 0x00
|
||||
0xcc4 0x02 0x00
|
||||
0xccc 0x09 0x00
|
||||
0xcd0 0xa2 0x00
|
||||
0xcd4 0x85 0x00
|
||||
0xc80 0xd1 0x00
|
||||
0xc84 0x1f 0x00
|
||||
0xc88 0x47 0x00
|
||||
0xcb8 0x75 0x00
|
||||
0xcbc 0x13 0x00
|
||||
0xcb0 0x86 0x00
|
||||
0xca0 0x04 0x00
|
||||
0xc8c 0x44 0x00
|
||||
0xc70 0xe7 0x00
|
||||
0xc74 0x03 0x00
|
||||
0xc78 0x40 0x00
|
||||
0xc7c 0x00 0x00
|
||||
0xdd8 0x88 0x00
|
||||
0xffffffff 0xffffffff 0x00>;
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<0xd74 /* USB3_PHY_PCS_STATUS */
|
||||
0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
|
||||
0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
|
||||
0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
|
||||
0xc00 /* USB3_PHY_SW_RESET */
|
||||
0xc08 /* USB3_PHY_START */
|
||||
0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
|
||||
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
|
||||
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||||
"ref_clk", "com_aux_clk", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
|
||||
reset-names = "phy_reset", "phy_phy_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_audio_qmi_dev {
|
||||
compatible = "qcom,usb-audio-qmi-dev";
|
||||
iommus = <&apps_smmu 0x172f 0x0>;
|
||||
qcom,usb-audio-stream-id = <0xf>;
|
||||
qcom,usb-audio-intr-num = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* Secondary USB port related controller */
|
||||
usb1: hsusb@a800000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa800000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
iommus = <&apps_smmu 0xE0 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
||||
"dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
qcom,default-mode-host;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
USB3_GDSC-supply = <&usb20_sec_gdsc>;
|
||||
clocks = <&gcc GCC_USB20_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_USB20_SEC_SLEEP_CLK>,
|
||||
<&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>;
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"xo", "sleep_clk", "utmi_clk";
|
||||
|
||||
resets = <&gcc GCC_USB20_SEC_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <120000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa800000 0xcd00>;
|
||||
interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
|
||||
linux,sysdev_is_parent;
|
||||
snps,disable-clk-gating;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x10>;
|
||||
snps,usb3_lpm_capable;
|
||||
usb-core-id = <1>;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* Secondary USB port related High Speed PHY */
|
||||
qusb_phy1: qusb@88e3000 {
|
||||
compatible = "qcom,qusb2phy";
|
||||
reg = <0x88e3000 0x180>,
|
||||
<0x01fcb3e4 0x4>;
|
||||
reg-names = "qusb_phy_base",
|
||||
"tcsr_conn_box_spare_0";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L13A>;
|
||||
qcom,vdd-voltage-level = <0 925000 975000>;
|
||||
qcom,qusb-phy-init-seq = <0xc8 0x80
|
||||
0xb3 0x84
|
||||
0x83 0x88
|
||||
0xc0 0x8c
|
||||
0x30 0x08
|
||||
0x79 0x0c
|
||||
0x21 0x10
|
||||
0x14 0x9c
|
||||
0x9f 0x1c
|
||||
0x00 0x18>;
|
||||
phy_type = "utmi";
|
||||
qcom,phy-clk-scheme = "cml";
|
||||
qcom,major-rev = <1>;
|
||||
qcom,hold-reset;
|
||||
|
||||
/* USB2PHY gets clock directly from CXO pad
|
||||
* connected to differential pin cxo_core_in_1p8_vdda.
|
||||
*/
|
||||
clocks = <&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>;
|
||||
clock-names = "ref_clk_src", "cfg_ahb_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
327
qcom/sa6155p-vm.dtsi
Normal file
327
qcom/sa6155p-vm.dtsi
Normal file
|
|
@ -0,0 +1,327 @@
|
|||
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
|
||||
#include <dt-bindings/clock/qcom,scc-sm6150.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "quin-vm-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine";
|
||||
qcom,msm-name = "SA6155P";
|
||||
qcom,msm-id = <377 0x0>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
CPU4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x4>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
CPU5: cpu@5 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x5>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
CPU6: cpu@6 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x6>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
CPU7: cpu@7 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x7>;
|
||||
capacity-dmips-mhz = <347>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
|
||||
core5 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&soc {
|
||||
VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL:
|
||||
pm6155_1_s2_level: regulator-pm6155-1-s2-level {
|
||||
compatible = "qcom,stub-regulator";
|
||||
regulator-name = "pm6155_1_s2_level";
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
apps_smmu: apps-smmu@0x15000000 {
|
||||
compatible = "qcom,qsmmu-v500";
|
||||
reg = <0x15000000 0x80000>,
|
||||
<0x150c2000 0x20>;
|
||||
reg-names = "base", "tcu-base";
|
||||
#iommu-cells = <2>;
|
||||
qcom,skip-init;
|
||||
qcom,use-3-lvl-tables;
|
||||
qcom,disable-atos;
|
||||
#global-interrupts = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
};
|
||||
|
||||
qcom_seecom: qseecom@86d00000 {
|
||||
compatible = "qcom,qseecom";
|
||||
reg = <0x86d00000 0xe00000>;
|
||||
reg-names = "secapp-region";
|
||||
memory-region = <&qseecom_mem>;
|
||||
qcom,hlos-num-ce-hw-instances = <1>;
|
||||
qcom,hlos-ce-hw-instance = <0>;
|
||||
qcom,qsee-ce-hw-instance = <0>;
|
||||
qcom,disk-encrypt-pipe-pair = <2>;
|
||||
qcom,no-clock-support;
|
||||
qcom,qsee-reentrancy-support = <2>;
|
||||
};
|
||||
|
||||
qcom_rng: qrng@793000 {
|
||||
compatible = "qcom,msm-rng";
|
||||
reg = <0x793000 0x1000>;
|
||||
qcom,no-qrng-config;
|
||||
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||
clock-names = "km_clk_src";
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sm6150-pdc";
|
||||
reg = <0xb220000 0x30000>;
|
||||
qcom,pdc-ranges = <6 486 1>, <8 488 4>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
®ulator {
|
||||
usb30_prim_gdsc: usb30_prim_gdsc {
|
||||
regulator-name = "usb30_prim_gdsc";
|
||||
};
|
||||
|
||||
usb20_sec_gdsc: usb20_sec_gdsc {
|
||||
regulator-name = "usb20_sec_gdsc";
|
||||
};
|
||||
|
||||
pcie_0_gdsc: pcie_0_gdsc {
|
||||
regulator-name = "pcie_0_gdsc";
|
||||
};
|
||||
|
||||
L2A: pm6155_1_l2: regulator-pm6155-1-l2 {
|
||||
regulator-name = "ldoa2";
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <3100000>;
|
||||
};
|
||||
|
||||
L5A: pm6155_1_l5: regulator-pm6155-1-l5 {
|
||||
regulator-name = "ldoa5";
|
||||
regulator-min-microvolt = <875000>;
|
||||
regulator-max-microvolt = <975000>;
|
||||
};
|
||||
|
||||
L10A: pm6155_1_l10: regulator-pm6155-1-l10 {
|
||||
regulator-name = "ldoa10";
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
};
|
||||
|
||||
L12A: pm6155_1_l12: regulator-pm6155-1-l12 {
|
||||
regulator-name = "ldoa12";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1890000>;
|
||||
};
|
||||
|
||||
L13A: pm6155_1_l13: regulator-pm6155-1-l13 {
|
||||
regulator-name = "ldoa13";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3230000>;
|
||||
};
|
||||
|
||||
S6A: pm6155_1_s6: regulator-pm6155-1-s6 {
|
||||
regulator-name = "smpa6";
|
||||
regulator-min-microvolt = <947000>;
|
||||
regulator-max-microvolt = <1404000>;
|
||||
};
|
||||
|
||||
S5A: pm6155_1_s5: regulator-pm6155-1-s5 {
|
||||
regulator-name = "smpa5";
|
||||
regulator-min-microvolt = <1896000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
L15A: pm6155_1_l15: regulator-pm6155-1-l15 {
|
||||
regulator-name = "ldoa15";
|
||||
regulator-min-microvolt = <1904000>;
|
||||
regulator-max-microvolt = <1904000>;
|
||||
};
|
||||
};
|
||||
|
||||
&firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
#include "sm6150-pinctrl.dtsi"
|
||||
#include "sa6155p-vm-usb.dtsi"
|
||||
#include "sa6155p-vm-pcie.dtsi"
|
||||
#include "sm6150-qupv3.dtsi"
|
||||
|
||||
&tlmm {
|
||||
/delete-property/ wakeup-parent;
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
/delete-property/ qcom,msm-bus,num-paths;
|
||||
/delete-property/ qcom,msm-bus,vectors-bus-ids;
|
||||
};
|
||||
|
||||
Loading…
Reference in a new issue