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ARM: dts: msm: Add Power management nodes for SDMSHRIKE
This change adds two items for power management. 1. Add PDC interrupt controller device. The interrupt map remains same as sm8150. Also mention PDC as wakeup parent for TLMM. 2. Include power management for sm8150 for APSS low power modes and various stats drivers. Change-Id: I3473f86bbaa3c289199d3ca88d0c31be5712f145
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2cbc4b940e
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2 changed files with 20 additions and 1 deletions
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@ -3,11 +3,20 @@
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compatible = "qcom,sdmshrike-pinctrl";
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reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>;
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reg-names = "pinctrl", "spi_cfg";
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interrupts =<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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ufs_dev_reset_assert: ufs_dev_reset_assert {
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config {
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@ -500,6 +500,15 @@
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interrupt-parent = <&intc>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8150-pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
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qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 1 0xf08>,
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@ -674,3 +683,4 @@
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#include "sdmshrike-pinctrl.dtsi"
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#include "sa8195-regulator.dtsi"
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#include "sm8150-pm.dtsi"
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