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ARM: dts: msm: refine QDSS config for sdxlemur

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Add reset and flush trigger number for etr and etf.

Change-Id: Iec420ee00ac45ca37e525f3736e0204d6c36e71b
This commit is contained in:
Yuanfang Zhang 2020-11-24 17:53:15 +08:00
commit 84870f513d
2 changed files with 7 additions and 2 deletions
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8
qcom/sdxlemur-coresight.dtsi
View file

@ -107,7 +107,9 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0_swao &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <1>;
clocks = <&aopcc QDSS_CLK>;
clock-names = "apb_pclk";
@ -147,7 +149,9 @@
arm,scatter-gather;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0 &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <3>;
coresight-csr = <&csr>;
clocks = <&aopcc QDSS_CLK>;

1
qcom/sdxlemur.dtsi
View file

@ -946,6 +946,7 @@
#include "sdxlemur-pinctrl.dtsi"
#include "sdxlemur-regulators.dtsi"
#include "sdxlemur-coresight.dtsi"
#include "msm-arm-smmu-sdxlemur.dtsi"
#include "sdxlemur-ion.dtsi"
#include "sdxlemur-usb.dtsi"