A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-09 05:39:54 -04:00
Code Issues Projects Releases Packages Wiki Activity

clk: qcom: gcc-shima: Update video_axi clks to clk_branch2_force_off_ops

Browse source 
SMMU fault is observed due to spurious AXI transaction even after
gcc video_axi clocks are disabled. HW underlying may not actually turn off
clocks since HW enable signals can still be asserted/waiting on certain
scenarios like when CVP and MVP both are power collapsed.
Use clk_branch2_force_off_ops to guarantee that clocks are actually
turned off when SW disables them.

Change-Id: Iaa9250a5962f3e74e971b4fc859d246960f792b0
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
This commit is contained in:
Jagadeesh Kona 2020-07-15 12:01:28 +05:30
commit 85247000b1
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
drivers/clk/qcom/gcc-shima.c
View file

@ -3184,7 +3184,7 @@ static struct clk_branch gcc_video_axi0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
.ops = &clk_branch2_force_off_ops,
},
},
};
@ -3199,7 +3199,7 @@ static struct clk_branch gcc_video_axi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
.ops = &clk_branch2_force_off_ops,
},
},
};