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ARM: dts: msm: Remove core clock reset for shima

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Remove core clock reset to be inline with lahaina sequence.

Change-Id: If6e9bde30ec4f73535bf53303805c43cb9b6f693
This commit is contained in:
Govindaraj Rajagopal 2020-07-16 13:39:01 +05:30 • committed by Gerrit - the friendly Code Review server
commit 8873580db9
1 changed files with 2 additions and 3 deletions
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5
qcom/shima-vidc.dtsi
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@ -26,9 +26,8 @@
qcom,clock-configs = <0x0 0x0 0x1 0x1>;
qcom,allowed-clock-rates = <240000000 338000000
364800000>;
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "video_axi_reset", "video_core_reset";
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
reset-names = "video_axi_reset";
qcom,reg-presets = <0xB0088 0x0 0x11>;