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Merge "clk: qcom: Update parent map to use parent_map struct"

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qctecmdr 2020-09-21 21:02:51 -07:00 • committed by Gerrit - the friendly Code Review server
commit 88dd3569e6
2 changed files with 21 additions and 12 deletions
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28
drivers/clk/qcom/clk-regmap-mux-div.c
View file

@ -56,20 +56,26 @@ int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
}
EXPORT_SYMBOL_GPL(mux_div_set_src_div);
static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
u32 *div)
int mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
u32 *div)
{
int ret = 0;
u32 val, d, s;
const char *name = clk_hw_get_name(&md->clkr.hw);
regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
if (ret)
return ret;
if (val & CMD_RCGR_DIRTY_CFG) {
pr_err("%s: RCG configuration is pending\n", name);
return;
return -EBUSY;
}
regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
ret = regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
if (ret)
return ret;
s = (val >> md->src_shift);
s &= BIT(md->src_width) - 1;
*src = s;
@ -77,6 +83,8 @@ static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
d = (val >> md->hid_shift);
d &= BIT(md->hid_width) - 1;
*div = d;
return ret;
}
static inline bool is_better_rate(unsigned long req, unsigned long best,
@ -142,7 +150,7 @@ static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
if (is_better_rate(rate, best_rate, actual_rate)) {
best_rate = actual_rate;
best_src = md->parent_map[i];
best_src = md->parent_map[i].cfg;
best_div = div - 1;
}
@ -169,7 +177,7 @@ static u8 mux_div_get_parent(struct clk_hw *hw)
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (src == md->parent_map[i])
if (src == md->parent_map[i].cfg)
return i;
pr_err("%s: Can't find parent with src %d\n", name, src);
@ -180,7 +188,7 @@ static int mux_div_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return mux_div_set_src_div(md, md->parent_map[index], md->div);
return mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
}
static int mux_div_set_rate(struct clk_hw *hw,
@ -197,7 +205,7 @@ static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return __mux_div_set_rate_and_parent(hw, rate, prate,
md->parent_map[index]);
md->parent_map[index].cfg);
}
static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
@ -209,7 +217,7 @@ static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < num_parents; i++)
if (src == md->parent_map[i]) {
if (src == md->parent_map[i].cfg) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
unsigned long parent_rate = clk_hw_get_rate(p);

5
drivers/clk/qcom/clk-regmap-mux-div.h
View file

@ -19,7 +19,7 @@
* @src_shift: lowest bit of source select field
* @div: the divider raw configuration value
* @src: the mux index which will be used if the clock is enabled
* @parent_map: map from parent_names index to src_sel field
* @parent_map: pointer to parent_map struct
* @clkr: handle between common and hardware-specific interfaces
* @pclk: the input PLL clock
* @clk_nb: clock notifier for rate changes of the input PLL
@ -32,7 +32,7 @@ struct clk_regmap_mux_div {
u32 src_shift;
u32 div;
u32 src;
const u32 *parent_map;
const struct parent_map *parent_map;
struct clk_regmap clkr;
struct clk *pclk;
struct notifier_block clk_nb;
@ -40,5 +40,6 @@ struct clk_regmap_mux_div {
extern const struct clk_ops clk_regmap_mux_div_ops;
extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
int mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src, u32 *div);
#endif