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clk: qcom: update the DisplayPort clocks

Browse source 
Update the frequencies of the clocks from Hz to KHz so that they
match the frequencies requested by the DisplayPort driver. This
ensures that the clock framework correctly scales parent clock
values for all DisplayPort clock requests.

Change-Id: I46be984340902f1facba59ad966e0f2ad1b1b006
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This commit is contained in:
Tatenda Chipeperekwa 2020-02-21 15:11:58 -08:00
commit 897ebf670e
1 changed files with 12 additions and 12 deletions
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24
drivers/clk/qcom/dispcc-lahaina.c
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@ -410,9 +410,9 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
.vdd_class = &vdd_mm,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 270000000,
[VDD_LOW_L1] = 540000000,
[VDD_NOMINAL] = 810000000},
[VDD_LOWER] = 270000,
[VDD_LOW_L1] = 540000,
[VDD_NOMINAL] = 810000},
},
};
@ -433,9 +433,9 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.vdd_class = &vdd_mm,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 270000000,
[VDD_LOW_L1] = 540000000,
[VDD_NOMINAL] = 810000000},
[VDD_LOWER] = 270000,
[VDD_LOW_L1] = 540000,
[VDD_NOMINAL] = 810000},
},
};
@ -456,8 +456,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.vdd_class = &vdd_mm,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 337500000,
[VDD_NOMINAL] = 675000000},
[VDD_LOWER] = 337500,
[VDD_NOMINAL] = 675000},
},
};
@ -478,8 +478,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
.vdd_class = &vdd_mm,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 337500000,
[VDD_NOMINAL] = 675000000},
[VDD_LOWER] = 337500,
[VDD_NOMINAL] = 675000},
},
};
@ -500,8 +500,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.vdd_class = &vdd_mm,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER] = 337500000,
[VDD_NOMINAL] = 675000000},
[VDD_LOWER] = 337500,
[VDD_NOMINAL] = 675000},
},
};