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Merge commit '30192b2f38' into remote

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Change-Id: Ibdc00a901ef46d8e23eb94895520ba99317ce655
This commit is contained in:
Naveen Kumar 2020-09-04 13:37:32 +05:30
commit 8d3f5f3913
109 changed files with 8461 additions and 635 deletions
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9
bindings/arm/coresight.txt
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@ -137,9 +137,10 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* Optional property for CATU :
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error
error for CATU and four interrupts for TGU to get trigger from four
type of events.
* Required property for TPDAs:
@ -480,6 +481,10 @@ Example:
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-timer-counters = <8>;
interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;
coresight-name = "coresight-tgu-ipcb";

39
bindings/arm/msm/hh_watchdog.yaml Normal file
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@ -0,0 +1,39 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/arm/msm/hh_watchdog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QTI HH Watchdog
maintainers:
description: |+
Watchdog timer is configured with a bark and a bite time.
If the watchdog is not "pet" at regular intervals, the system
is assumed to have become non responsive and needs to be reset.
A warning in the form of a bark timeout leads to a bark interrupt
and a kernel panic. If the watchdog timer is still not reset,
a bite timeout occurs, which leads to a reset of the VM via
the hypervisor. The driver needs the petting time, and the bark
timeout to be programmed into the watchdog, as well as the bark irq.
The device tree parameters for the watchdog are:
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,hh-watchdog"
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should contain the bark irq number
example:
- |
wdog_hh: qcom,wdt_hh {
compatible = "qcom,hh-watchdog";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};
...

3
bindings/arm/msm/imem.yaml
View file

@ -69,6 +69,9 @@ patternProperties:
- const: qcom,msm-imem-diag-dload
description: USB Diag download mode region
- const: qcom,msm-imem-pil-disable-timeout
description: Offset to set PIL debug cookie
reg:
description: Start address and the size of the region

3
bindings/arm/msm/lpm-levels.txt
View file

@ -29,6 +29,7 @@ Required properties:
Optional properties:
- reg: The address range
- reg-names: Specifies the address field names.
- qcom,disable-prediction: This property is used to indicate the LPM
governor will not use LPM prediction for this cluster.
- qcom,clstr-tmr-add: This property is used as correction timer for
@ -86,6 +87,8 @@ that share the parameters.It contains the following properties.
Optional properties:
- qcom,disable-prediction: This property is used to indicate the
LPM governor is to disable sleep prediction to this cpu.
- label: Identifies the cluster name. The name is used when parsing the
RIMPS addresses.
- qcom,ref-stddev: This property is used as reference standard deviation
in lpm prediction algorithm. This value should be between 100 to 1000.
Higher value would result in more predictions and thereby resulting in

33
bindings/arm/msm/msm_watchdog.yaml
View file

@ -44,35 +44,6 @@ properties:
Value type: <prop-encoded-array>
Definition: should contain bark and bite irq numbers
qcom,pet-time:
Usage: required
Value type: <u32>
Definition: Non zero time interval at which watchdog should be pet in ms.
qcom,bark-time:
Usage: required
Value type: <u32>
Definition: Non zero timeout value for a watchdog bark in ms.
qcom,userspace-watchdog:
Usage: optional
Value type: <boolean>
Definition: Allow enabling the userspace-watchdog feature. This feature
requires userspace to pet the watchdog every qcom,pet-time interval
in addition to the existing kernel-level checks.
This feature is supported through device sysfs files.
qcom,ipi-ping:
Usage: optional
Value type: <boolean>
Definition: send keep alive ping to other cpus if present
qcom,wakeup-enable:
Usage: optional
Value type: <boolean>
Definition: enable non secure watchdog to freeze / unfreeze
automatically across suspend / resume path.
example:
- |
wdog: qcom,wdt@17c10000{
@ -81,9 +52,5 @@ example:
reg-names = "wdt-base";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
<0 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
};
...

2
bindings/arm/msm/qcom,llcc.txt
View file

@ -12,7 +12,7 @@ Properties:
Usage: required
Value type: <string>
Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
or "qcom,shima-llcc".
or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
"qcom,llcc-v2" must be appended for V2 hardware.
- reg:

8
bindings/cpufreq/cpufreq-qcom-hw.txt
View file

@ -42,6 +42,14 @@ Properties:
Definition: Indicate to check for Enable of FW before registering
with cpufreq.
- qcom,perf-lock-support
Usage: Optional
Value type: bool
Definition: Indicate to check for performance lock support in FW.
In case this property is present, the reg & reg-names
should have the "pdmem-domainX" to indicate the
corresponding bases.
* Property qcom,freq-domain
Devices supporting freq-domain must set their "qcom,freq-domain" property with
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

35
bindings/interconnect/qcom,cpucp-l3.txt Normal file
View file

@ -0,0 +1,35 @@
Qualcomm Technologies, Inc. CPUCP L3 interconnect driver binding
-----------------------------------------------------------
The CPUCP L3 Interconnect provider supports the scaling of L3 cache
performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,holi-cpucp-l3-shared",
"qcom,holi-cpucp-l3-cpu";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
- clocks: list of phandle and clock specifier pairs corresponding to
entries in the clock-names property.
- #interconnect-cells : should contain 1
Examples:
cpucp_l3_shared: l3_shared@fd90000 {
reg = <0x0fd90000 0x3000>;
compatible = "qcom,holi-cpucp-l3-shared";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPLL0>;
};
cpucp_l3_cpu: l3_cpu@fd90000{
reg = <0x0fd90000 0x3000>;
compatible = "qcom,holi-cpucp-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPLL0>;
};

1
bindings/interconnect/qcom,epss-l3.txt
View file

@ -8,7 +8,6 @@ Required properties :
- compatible : shall contain only one of the following:
"qcom,lahaina-epss-l3-shared",
"qcom,lahaina-epss-l3-cpu",
"qcom,holi-epss-l3-cpu",
"qcom,shima-epss-l3-cpu",
"qcom,shima-epss-l3-shared";
- reg : Address and length of the register set for the device

7
bindings/interconnect/qcom,holi.txt
View file

@ -15,6 +15,12 @@ reg : specifies the physical base address and size of registers
clocks : list of phandles and specifiers to all interconnect bus clocks
clock-names : clock names should include both "bus" and "bus_a"
The following are optional properties:
qcom,util-factor : Parameter that represents the DDR utilization factor
to be used in aggregation scheme. It is represented as
actual util-factor * 100.
Examples:
soc {
@ -22,6 +28,7 @@ soc {
system_noc: interconnect@1880000 {
reg = <0x1880000 0x5f080>;
compatible = "qcom,holi-system_noc";
qcom,util-factor = <142>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,

2
bindings/pinctrl/qcom,pmic-gpio.txt
View file

@ -32,6 +32,7 @@ PMIC's from Qualcomm.
"qcom,pm7250b-gpio"
"qcom,pm6350-gpio"
"qcom,pm6150l-gpio"
"qcom,pmx65-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@ -118,6 +119,7 @@ to specify in a pin configuration subnode:
gpio1-gpio12 for pm7250b
gpio1-gpio9 for pm6350
gpio1-gpio12 for pm6150l
gpio1-gpio16 for pmx65
- function:
Usage: required

25
bindings/power/supply/qcom/qpnp-qg.txt
View file

@ -19,13 +19,20 @@ First Level Node - QGAUGE device
- compatible
Usage: required
Value type: <string>
Definition: Should be "qcom,qpnp-qg" or "qcom,qpnp-qg-lite".
Definition: Should be "qcom,qpnp-qg-lite" for PM2250.
Should be "qcom,pm6150-qg" for PM6150.
Should be "qcom,pmi632-qg" for PMI632.
Should be "qcom,pm7250b-qg" for PM7250B.
- qcom,pmic-revid
- io-channels
Usage: required
Value type: <phandle>
Definition: Should specify the phandle of PMIC revid module. This is
used to identify the PMIC subtype.
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
- io-channel-names
Usage: required
Value type: <string-array>
Definition: Names of the IIO channels that are used by QG device.
- qcom,qg-vadc
Usage: required
@ -473,13 +480,17 @@ Example
========
pmi632_qg: qpnp,qg {
compatible = "qcom,qpnp-qg";
qcom,pmic-revid = <&pmi632_revid>;
compatible = "qcom,pm7250b-qg";
qcom,qg-vadc = <&pmi632_vadc>;
qcom,vbatt-empty-mv = <3200>;
qcom,vbatt-low-mv = <3500>;
qcom,vbatt-cutoff-mv = <3400>;
qcom,qg-iterm-ma = <100>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "recharge_soc",
"charge_done";
qcom,qgauge@4800 {
status = "okay";

31
bindings/power/supply/qcom/qpnp-smb5.txt
View file

@ -19,13 +19,19 @@ Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,qpnp-smb5".
Definition: "qcom,pm8150-smb5" for SMB5 on PM8150.
"qcom,pm7250b-smb5" for SMB5 on PM7250B.
"qcom,pm6150-smb5" for SMB5 on PM6150.
"qcom,pmi632-smb5" for SMB5 on PMI632.
- qcom,pmic-revid
Usage: required
Value type: phandle
Definition: Should specify the phandle of PMI's revid module. This is used to
identify the PMI subtype.
- #io-channel-cells:
Usage: required
Value type: <u32>
Definition: Number of cells in an IIO specifier.
Needed to indicate other clients can query charger for
IIO channels.
For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,sec-charger-config
Usage: optional
@ -419,8 +425,7 @@ pm8150b_charger: qcom,qpnp-smb5 {
compatible = "qcom,qpnp-smb5";
#address-cells = <1>;
#size-cells = <1>;
qcom,pmic-revid = <&pm8150b_revid>;
#io-channel-cells = <1>;
dpdm-supply = <&qusb_phy0>;
@ -428,10 +433,16 @@ pm8150b_charger: qcom,qpnp-smb5 {
io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>,
<&pm8150b_vadc ADC_USB_IN_I>,
<&pm8150b_vadc ADC_CHG_TEMP>;
<&pm8150b_vadc ADC_CHG_TEMP>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp";
"chg_temp",
"resistance_id",
"charge_counter",
"charge_full";
qcom,chgr@1000 {
reg = <0x1000 0x100>;

28
bindings/soc/qcom/qcom,pmic-pon-log.txt Normal file
View file

@ -0,0 +1,28 @@
Qualcomm Technologies, Inc. PMIC PON Log
Certain Qualcomm Technologies, Inc. PMIC devices capture power-on, power-off,
and fault information in a binary log found within SDAM peripherals. The PMIC
PON Log device accesses this log and parses it into a human readable format.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,pmic-pon-log"
- nvmem:
Usage: required
Value type: <phandle-list>
Definition: phandle of the PMIC nvmem device containing the PON log
- nvmem-names:
Usage: required
Value type: <stringlist>
Definition: must be "pon_log"
Example:
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};

3
bindings/usb/qcom,dwc3.txt
View file

@ -23,9 +23,6 @@ Optional clocks:
Not present on "qcom,msm8996-dwc3" compatible.
"cfg_noc" System Config NOC clock.
Not present on "qcom,msm8996-dwc3" compatible.
"core_csr" Allows to set/clear FORCE_MEM_CORE_ON with USB core
clock to retain USB controller CSR across system deep
sleep.
- assigned-clocks: Should be:
MOCK_UTMI_CLK
MASTER_CLK

71
bindings/usb/qpnp-pdphy.txt Normal file
View file

@ -0,0 +1,71 @@
Qualcomm Technologies, Inc. QPNP PD PHY - USB Power Delivery Physical layer
Required properties:
- compatible: Must be "qcom,qpnp-pdphy"
- reg: The base address for this peripheral
- vdd-pdphy-supply: phandle to the VDD supply regulator node
- interrupts: Specifies the interrupt associated with the peripheral.
- interrupt-names: Specifies the interrupt names for the peripheral. Every
available interrupt needs to have an associated name
with it to indentify its purpose.
The following interrupts are required:
0: sig-tx
Triggers when a signal (HardReset or CableReset)
has been sent.
1: sig-rx
Triggers when a signal has been received.
2: msg-tx
Triggers when a message has been sent and the
related GoodCRC has been received.
3: msg-rx
Triggers when a message has been received and
the related GoodCRC was sent successfully.
4: msg-tx-failed
Triggers when a message failed all its
transmission attempts, either due to a non-idle
bus or missing GoodCRC reply.
5: msg-tx-discarded
Triggers when a message is received while a
transmission request was in place. The request
itself is discarded.
6: msg-rx-discarded
Triggers when a message was received but had to
be discarded due to the RX buffer still in use
by SW.
Optional properties:
- vbus-supply: Regulator that enables VBUS source output
- vconn-supply: Regulator that enables VCONN source output. This will
be supplied on the USB CC line that is not used for
communication when Ra resistance is detected.
- qcom,default-sink-caps: List of 32-bit values representing the nominal sink
capabilities in voltage (millivolts) and current
(milliamps) pairs.
Example:
qcom,qpnp-pdphy@1700 {
compatible = "qcom,qpnp-pdphy";
reg = <0x1700 0x100>;
vdd-pdphy-supply = <&pm8998_l24>;
interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sig-tx",
"sig-rx",
"msg-tx",
"msg-rx",
"msg-tx-failed",
"msg-tx-discarded",
"msg-rx-discarded";
qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
<9000 3000>, /* 9V @ 3A */
<12000 2250>; /* 12V @ 2.25A */
};

13
qcom/Makefile
View file

@ -141,7 +141,9 @@ endif
ifeq ($(CONFIG_ARCH_LAHAINA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
dtb-$(CONFIG_ARCH_QTI_VM) += trustedvm.dtb
dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \
lahaina-vm-cdp.dtb \
lahaina-vm-qrd.dtb
endif
endif
@ -149,6 +151,15 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \
sdxlemur-cdp.dtb \
sdxlemur-mtp.dtb
ifeq ($(CONFIG_ARCH_SHIMA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \
shima-vm-atp.dtb \
shima-vm-idp.dtb \
shima-vm-qrd.dtb
endif
endif
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

136
qcom/holi-atp.dtsi
View file

@ -3,6 +3,7 @@
#include "holi-pmic-overlay.dtsi"
#include "display/holi-sde-display-atp.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok"
@ -80,6 +81,9 @@
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
@ -125,6 +129,88 @@
status = "ok"
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,batteryless-platform;
qcom,sec-charger-config = <0>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
};
&pm7250b_qg {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
};
&qupv3_se8_i2c {
status = "okay";
qcom,i2c-touch-active="synaptics,tcm-i2c";
@ -158,3 +244,53 @@
&dsi_rm69299_visionox_amoled_cmd>;
};
};
&pm7250b_charger {
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

1
qcom/holi-audio-overlay.dtsi
View file

@ -33,6 +33,7 @@
qcom,va-swr-gpios = <&va_swr_gpios>;
swr0: va_swr_master {
compatible = "qcom,swr-mstr";
qcom,is_wcd937x = <1>;
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";

136
qcom/holi-cdp.dtsi
View file

@ -4,6 +4,7 @@
#include "holi-pmic-overlay.dtsi"
#include "display/holi-sde-display-cdp.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok"
@ -81,6 +82,9 @@
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
@ -114,6 +118,88 @@
status = "ok"
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,batteryless-platform;
qcom,sec-charger-config = <0>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
};
&pm7250b_qg {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,qg-iterm-ma = <100>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
};
&qupv3_se8_i2c {
status = "okay";
qcom,i2c-touch-active="synaptics,tcm-i2c";
@ -149,3 +235,53 @@
};
#include "camera/holi-camera-sensor-cdp.dtsi"
&pm7250b_charger {
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

6
qcom/holi-coresight.dtsi
View file

@ -45,9 +45,9 @@
reg-names = "tgu-base";
tgu-steps = <3>;
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-regs = <8>;
tgu-timer-counters = <8>;
interrupts = <0 23 1>, <0 24 1>, <0 25 1>, <0 26 1>;
coresight-name = "coresight-tgu-apss";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
@ -1958,7 +1958,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
coresight-ctis = <&cti0 &cti6>;
in-ports {
port {
tmc_etf_in_funnel_merge: endpoint {

9
qcom/holi-ion.dtsi
View file

@ -16,6 +16,15 @@
qcom,ion-heap-type = "SYSTEM_SECURE";
};
qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
reg = <ION_SECURE_CARVEOUT_HEAP_ID>;
qcom,ion-heap-type = "SECURE_CARVEOUT";
cdsp {
memory-region = <&cdsp_secure_heap_mem>;
token = <0x20000000>;
};
};
qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
reg = <ION_SECURE_DISPLAY_HEAP_ID>;
memory-region = <&secure_display_memory>;

152
qcom/holi-mtp-usbc.dtsi
View file

@ -2,6 +2,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "holi-pmic-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok"
@ -92,8 +93,159 @@
linux,can-disable;
};
};
mtp_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
#include "qg-batterydata-alium-3600mah.dtsi"
#include "qg-batterydata-atl466271_3300mAh.dtsi"
#include "qg-batterydata-atl436186020H_3780mAh.dtsi"
};
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
qcom,fcc-stepping-enable;
qcom,fcc-step-delay-ms = <100>;
qcom,fcc-step-size-ua = <100000>;
qcom,smb-internal-pull-kohm = <0>;
qcom,en-skin-therm-mitigation;
qcom,hvdcp3-standalone-config;
};
&pm7250b_qg {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,battery-data = <&mtp_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
qcom,tcss-enable;
qcom,fvss-enable;
qcom,fvss-vbatt-mv = <3300>;
qcom,bass-enable;
qcom,use-cp-iin-sns;
};
&pm6150a_amoled {
status = "ok"
};
&pm7250b_charger {
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

155
qcom/holi-mtp.dtsi
View file

@ -4,6 +4,7 @@
#include "holi-pmic-overlay.dtsi"
#include "display/holi-sde-display-mtp.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok"
@ -81,6 +82,9 @@
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
@ -108,6 +112,13 @@
linux,can-disable;
};
};
mtp_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
#include "qg-batterydata-alium-3600mah.dtsi"
#include "qg-batterydata-atl466271_3300mAh.dtsi"
#include "qg-batterydata-atl436186020H_3780mAh.dtsi"
};
};
&pm6150a_amoled {
@ -148,4 +159,148 @@
};
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
qcom,fcc-stepping-enable;
qcom,fcc-step-delay-ms = <100>;
qcom,fcc-step-size-ua = <100000>;
qcom,smb-internal-pull-kohm = <0>;
qcom,en-skin-therm-mitigation;
qcom,hvdcp3-standalone-config;
};
&pm7250b_qg {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,battery-data = <&mtp_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
qcom,tcss-enable;
qcom,fvss-enable;
qcom,fvss-vbatt-mv = <3300>;
qcom,bass-enable;
qcom,use-cp-iin-sns;
};
#include "camera/holi-camera-sensor-mtp.dtsi"
&pm7250b_charger {
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

3
qcom/holi-pm.dtsi
View file

@ -2,6 +2,7 @@
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
reg = <0xfd91060 0x20>, <0xfd92060 0x20>;
reg-names = "pwr", "perf";
#address-cells = <1>;
#size-cells = <0>;
@ -45,6 +46,7 @@
#size-cells = <0>;
qcom,psci-mode-shift = <0>;
qcom,psci-mode-mask = <0xf>;
label = "pwr";
qcom,ref-stddev = <500>;
qcom,tmr-add = <1000>;
qcom,ref-premature-cnt = <1>;
@ -98,6 +100,7 @@
#size-cells = <0>;
qcom,psci-mode-shift = <0>;
qcom,psci-mode-mask = <0xf>;
label = "perf";
qcom,ref-stddev = <100>;
qcom,tmr-add = <100>;
qcom,ref-premature-cnt = <3>;

15
qcom/holi-pmic-overlay.dtsi
View file

@ -1,5 +1,6 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/iio/qti_power_supply_iio.h>
#include "pm6350.dtsi"
#include "pm7250b.dtsi"
@ -244,6 +245,20 @@
};
};
&flash_led {
status = "ok"
io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_charger PSY_IIO_FLASH_TRIGGER>,
<&pm7250b_charger PSY_IIO_FLASH_ACTIVE>;
io-channel-names = "rbatt",
"voltage_ocv",
"current_now",
"flash_trigger",
"flash_active";
};
&thermal_zones {
chg-skin-therm-usr {
polling-delay-passive = <0>;

156
qcom/holi-qrd.dtsi
View file

@ -5,6 +5,7 @@
#include "holi-thermal-overlay.dtsi"
#include "camera/holi-camera-sensor-qrd.dtsi"
#include "display/holi-sde-display-qrd.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok"
@ -82,6 +83,9 @@
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
@ -217,8 +221,160 @@
linux,can-disable;
};
};
qrd_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
#include "qg-batterydata-atl436186020H_3780mAh.dtsi"
#include "qg-batterydata-atl466271_3300mAh.dtsi"
};
};
&pm6150a_amoled {
status = "ok"
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,battery-data = <&qrd_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
qcom,fcc-stepping-enable;
qcom,fcc-step-delay-ms = <100>;
qcom,fcc-step-size-ua = <100000>;
qcom,smb-internal-pull-kohm = <0>;
qcom,en-skin-therm-mitigation;
qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
7500000 7000000 6500000 6000000 5500000 5000000 4500000
4000000 3500000 3000000 2500000 2000000 1500000 1000000
500000>;
};
&pm7250b_qg {
status = "ok"
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
qcom,tcss-enable;
qcom,fvss-enable;
qcom,fvss-vbatt-mv = <3300>;
qcom,bass-enable;
qcom,use-cp-iin-sns;
};
&pm7250b_charger {
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

1
qcom/holi-qupv3.dtsi
View file

@ -318,6 +318,7 @@
dmas = <&gpi_dma1 0 4 3 64 0>,
<&gpi_dma1 1 4 3 64 0>;
dma-names = "tx", "rx";
qcom,shared;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};

46
qcom/holi-regulators.dtsi
View file

@ -6,7 +6,7 @@
S1A: pm6350_s1: regulator-s1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1000000>;
qcom,init-voltage = <1128000>;
status = "okay";
};
};
@ -16,7 +16,7 @@
S2A: pm6350_s2: regulator-s2 {
regulator-min-microvolt = <1503000>;
regulator-max-microvolt = <2048000>;
qcom,init-voltage = <1503000>;
qcom,init-voltage = <2040000>;
status = "okay";
};
};
@ -50,7 +50,7 @@
qcom,use-voltage-level;
};
gfx_cdev: gfx-reg-cdev {
gfx_cdev: gfx-cdev {
compatible = "qcom,regulator-cooling-device";
regulator-cdev-supply = <&VDD_GFX_LEVEL_AO>;
regulator-levels = <RPM_SMD_REGULATOR_LEVEL_RETENTION
@ -141,7 +141,7 @@
L2A: pm6350_l2: regulator-l2 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1620000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
@ -151,7 +151,7 @@
L3A: pm6350_l3: regulator-l3 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2700000>;
qcom,init-voltage = <3080000>;
status = "okay";
};
};
@ -161,7 +161,7 @@
L4A: pm6350_l4: regulator-l4 {
regulator-min-microvolt = <352000>;
regulator-max-microvolt = <801000>;
qcom,init-voltage = <352000>;
qcom,init-voltage = <704000>;
status = "okay";
};
};
@ -198,10 +198,13 @@
rpm-regulator-ldoa8 {
status = "okay";
proxy-supply = <&pm6350_l8>;
L8A: pm6350_l8: regulator-l8 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2500000>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <857000>;
status = "okay";
};
};
@ -231,7 +234,7 @@
L11A: pm6350_l11: regulator-l11 {
regulator-min-microvolt = <1503000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1503000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
@ -241,7 +244,7 @@
L12A: pm6350_l12: regulator-l12 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1620000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
@ -251,7 +254,7 @@
L13A: pm6350_l13: regulator-l13 {
regulator-min-microvolt = <570000>;
regulator-max-microvolt = <650000>;
qcom,init-voltage = <570000>;
qcom,init-voltage = <600000>;
status = "okay";
};
};
@ -271,7 +274,7 @@
L15A: pm6350_l15: regulator-l15 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1305000>;
qcom,init-voltage = <1100000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
@ -281,7 +284,7 @@
L16A: pm6350_l16: regulator-l16 {
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <921000>;
qcom,init-voltage = <830000>;
qcom,init-voltage = <880000>;
status = "okay";
};
};
@ -309,7 +312,7 @@
L18A: pm6350_l18: regulator-l18 {
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1049000>;
qcom,init-voltage = <788000>;
qcom,init-voltage = <880000>;
status = "okay";
};
};
@ -349,7 +352,7 @@
L22A: pm6350_l22: regulator-l22 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1305000>;
qcom,init-voltage = <1080000>;
qcom,init-voltage = <1232000>;
status = "okay";
};
};
@ -365,7 +368,7 @@
BOB: pm6150a_bob: regulator-pm6150a-bob {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <5500000>;
qcom,init-voltage = <1650000>;
qcom,init-voltage = <3296000>;
qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_PASS>;
status = "okay";
};
@ -373,7 +376,7 @@
BOB_AO: pm6150a_bob_ao: regulator-pm6150a-bob-ao {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <5500000>;
qcom,init-voltage = <1650000>;
qcom,init-voltage = <3296000>;
qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_AUTO>;
status = "okay";
};
@ -443,17 +446,20 @@
S8E: pm6150a_s8: regulator-s8 {
regulator-min-microvolt = <313000>;
regulator-max-microvolt = <1395000>;
qcom,init-voltage = <313000>;
qcom,init-voltage = <1352000>;
status = "okay";
};
};
rpm-regulator-ldoe1 {
status = "okay";
proxy-supply = <&pm6150a_l1>;
L1E: pm6150a_l1: regulator-l1 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1650000>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <62000>;
status = "okay";
};
};
@ -503,7 +509,7 @@
L6E: pm6150a_l6: regulator-l6 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <1700000>;
qcom,init-voltage = <2960000>;
status = "okay";
};
};
@ -513,7 +519,7 @@
L7E: pm6150a_l7: regulator-l7 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-voltage = <2960000>;
status = "okay";
};
};
@ -533,7 +539,7 @@
L9E: pm6150a_l9: regulator-l9 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-voltage = <2960000>;
status = "okay";
};
};
@ -565,5 +571,7 @@
reg = <0x162F000 0x60>;
regulator-name = "refgen";
regulator-enable-ramp-delay = <5>;
proxy-supply = <&refgen>;
qcom,proxy-consumer-enable;
};
};

22
qcom/holi-thermal-overlay.dtsi
View file

@ -4,6 +4,10 @@
#cooling-cells = <2>;
};
&pm7250b_charger {
#cooling-cells = <2>;
};
&thermal_zones {
socd {
cooling-maps {
@ -19,6 +23,24 @@
};
};
pm7250b_tz {
cooling-maps {
battery_cdev0 {
trip = <&pm7250b_trip0>;
cooling-device =
<&pm7250b_charger (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
};
battery_cdev1 {
trip = <&pm7250b_trip1>;
cooling-device =
<&pm7250b_charger THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
pm6350_tz {
cooling-maps {
trip0_cpu0 {

6
qcom/holi-usb.dtsi
View file

@ -16,9 +16,9 @@
ranges;
dma-ranges;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<&wakegic 12 IRQ_TYPE_LEVEL_HIGH>,
<&wakegic 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,

278
qcom/holi.dtsi
View file

@ -2,7 +2,7 @@
#include <dt-bindings/clock/qcom,gcc-holi.h>
#include <dt-bindings/clock/qcom,gpucc-holi.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,cpucp-l3.h>
#include <dt-bindings/interconnect/qcom,holi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -335,6 +335,16 @@
size = <0 0x800000>;
};
splash_memory: splash_region@0x85200000 {
reg = <0x0 0x85200000 0x0 0x00c00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@85e00000 {
reg = <0x0 0x85e00000 0x0 0x00100000>;
label = "dfps_data_region";
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
@ -387,6 +397,11 @@
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
@ -394,7 +409,7 @@
dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
@ -651,72 +666,72 @@
};
l1_icache0 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x60>;
};
l1_icache1 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x61>;
};
l1_icache2 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x62>;
};
l1_icache3 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x63>;
};
l1_icache100 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x64>;
};
l1_icache101 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x10800>;
qcom,dump-id = <0x65>;
};
l1_icache102 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x21000>;
qcom,dump-id = <0x66>;
};
l1_icache103 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x21000>;
qcom,dump-id = <0x67>;
};
l1_dcache0 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x80>;
};
l1_dcache1 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x81>;
};
l1_dcache2 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x82>;
};
l1_dcache3 {
qcom,dump-size = <0x9040>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x83>;
};
l1_dcache100 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x84>;
};
l1_dcache101 {
qcom,dump-size = <0x12000>;
qcom,dump-size = <0x9000>;
qcom,dump-id = <0x85>;
};
@ -731,42 +746,42 @@
};
l2_tlb0 {
qcom,dump-size = <0x2000>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x120>;
};
l2_tlb1 {
qcom,dump-size = <0x2000>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x121>;
};
l2_tlb2 {
qcom,dump-size = <0x2000>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x122>;
};
l2_tlb3 {
qcom,dump-size = <0x2000>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x123>;
};
l2_tlb100 {
qcom,dump-size = <0x4800>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x124>;
};
l2_tlb101 {
qcom,dump-size = <0x4800>;
qcom,dump-size = <0x5a00>;
qcom,dump-id = <0x125>;
};
l2_tlb102 {
qcom,dump-size = <0x4800>;
qcom,dump-size = <0x7800>;
qcom,dump-id = <0x126>;
};
l2_tlb103 {
qcom,dump-size = <0x4800>;
qcom,dump-size = <0x7800>;
qcom,dump-id = <0x127>;
};
@ -776,7 +791,7 @@
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-size = <0x2c000>;
qcom,dump-id = <0xea>;
};
@ -819,6 +834,16 @@
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
};
fsm_data {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x165>;
};
};
qcom,msm-imem@c125000 {
@ -858,6 +883,11 @@
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
@ -907,7 +937,7 @@
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
@ -932,37 +962,43 @@
<&rpmcc RPM_SMD_QUP_A_CLK>;
};
system_noc: interconnect@1880000 {
reg = <0x01880000 0x1900>;
compatible = "qcom,holi-system_noc";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
mmnrt_virt: interconnect@1899000 {
reg = <0x01899000 0x6000>;
mmnrt_virt: interconnect@0 {
compatible = "qcom,holi-mmnrt_virt";
#interconnect-cells = <1>;
qcom,util-factor = <142>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
};
mmrt_virt: interconnect@189f000 {
reg = <0x0189f000 0x1000>;
mmrt_virt: interconnect@1 {
compatible = "qcom,holi-mmrt_virt";
#interconnect-cells = <1>;
qcom,util-factor = <142>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
<&rpmcc RPM_SMD_MMRT_A_CLK>;
};
system_noc: interconnect@1880000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01880000 0x5f080>;
compatible = "qcom,holi-system_noc";
#interconnect-cells = <1>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
config_noc: interconnect@1900000 {
reg = <0x01900000 0x6200>;
compatible = "qcom,holi-config_noc";
#interconnect-cells = <1>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
@ -972,18 +1008,19 @@
reg = <0x04480000 0x80000>;
compatible = "qcom,holi-bimc";
#interconnect-cells = <1>;
qcom,util-factor = <151>;
qcom,keepalive;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
epss_l3_cpu: l3_cpu@fd91000 {
reg = <0x0fd91000 0x4000>;
compatible = "qcom,holi-epss-l3-cpu";
cpucp_l3_cpu: l3_cpu@fd90000 {
reg = <0x0fd90000 0x3000>;
compatible = "qcom,holi-cpucp-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
status = "disabled";
};
qcom,memshare {
@ -1013,6 +1050,94 @@
};
};
jtag_mm0: jtagmm@9040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9040000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@9140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9140000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@9240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9240000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@9340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9340000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@9440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9440000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@9540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9540000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@9640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9640000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@9740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x9740000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
@ -1102,13 +1227,19 @@
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>,
<0x0fd04504 0x4>, <0x0fd04508 0x4>;
reg-names = "freq-domain0", "freq-domain1",
"pdmem-domain0", "pdmem-domain1";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,max-lut-entries = <12>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";
#freq-domain-cells = <2>;
};
@ -1152,8 +1283,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>;
};
cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
@ -1162,8 +1293,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>;
};
cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
@ -1172,8 +1303,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>;
};
cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
@ -1182,8 +1313,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>;
};
cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
@ -1192,8 +1323,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>;
};
cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
@ -1202,12 +1333,12 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>;
};
cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
compatible = "qcom,devfreq-icc";
governor = "compute";
interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>;
qcom,active-only;
@ -1220,8 +1351,8 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>;
};
cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
@ -1230,12 +1361,12 @@
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>;
};
cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>;
qcom,active-only;
@ -1243,7 +1374,7 @@
};
cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>;
qcom,active-only;
@ -1251,7 +1382,7 @@
};
cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
compatible = "qcom,devfreq-icc";
governor = "compute";
interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>;
qcom,active-only;
@ -1739,7 +1870,7 @@
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_LOW>,
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
};
@ -2028,8 +2159,12 @@
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "ice_core";
qcom,ice-clk-rates = <300000000 100000000>;
interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>;
@ -2390,9 +2525,12 @@
interrupt-names = "eud_irq";
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1628000 0x2000>,
<0x162A000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
<0x162A000 0x1000>,
<0x3E5018 0x4>;
reg-names = "eud_base", "eud_mode_mgr2",
"eud_tcsr_check_reg";
qcom,secure-eud-en;
qcom,eud-tcsr-check-enable;
status = "ok"
};

18
qcom/lahaina-audio-overlay.dtsi
View file

@ -317,6 +317,10 @@
"TX SWR_INPUT", "SWR_MIC1 SWR_DMIC_OUTPUT",
"TX SWR_INPUT", "SWR_MIC2 SWR_DMIC_OUTPUT",
"TX SWR_INPUT", "SWR_MIC3 SWR_DMIC_OUTPUT",
"VA SWR_INPUT", "SWR_MIC0 SWR_DMIC_VA_OUTPUT",
"VA SWR_INPUT", "SWR_MIC1 SWR_DMIC_VA_OUTPUT",
"VA SWR_INPUT", "SWR_MIC2 SWR_DMIC_VA_OUTPUT",
"VA SWR_INPUT", "SWR_MIC3 SWR_DMIC_VA_OUTPUT",
"VA SWR_INPUT", "SWR_MIC0 SWR_DMIC_OUTPUT",
"VA SWR_INPUT", "SWR_MIC1 SWR_DMIC_OUTPUT",
"VA SWR_INPUT", "SWR_MIC2 SWR_DMIC_OUTPUT",
@ -355,16 +359,22 @@
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>,
<&swr_dmic_01>, <&swr_dmic_02>,
<&swr_dmic_03>, <&swr_dmic_04>,
<&swr_dmic_04>, <&swr_dmic_03>,
<&swr_dmic_02>, <&swr_dmic_01>,
<&ext_disp_audio_codec>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2",
"swr-dmic.01", "swr-dmic.02",
"swr-dmic.03", "swr-dmic.04",
"swr-dmic.04", "swr-dmic.03",
"swr-dmic.02", "swr-dmic.01",
"msm-ext-disp-audio-codec-rx";
qcom,wsa-max-devs = <2>;
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>;
qcom,cps_threshold_levels = <148 168>;
qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
qcom,cps_lower2_values = <0x0F 0x0F 0x18>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
};

19
qcom/lahaina-cdp.dtsi
View file

@ -77,7 +77,7 @@
st,touch-environment = "pvm";
st,trusted-touch-spi-irq = <566>;
st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
&dsi_sw43404_amoled_fhd_plus_cmd>;
};
@ -201,17 +201,20 @@
status = "ok"
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
&q6core {
cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
};
&lahaina_snd {
qcom,model = "lahaina-cdp-snd-card";
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
};
&usb1 {

3
qcom/lahaina-coresight.dtsi
View file

@ -107,6 +107,7 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0 &cti6>;
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@ -153,7 +154,7 @@
qcom,sw-usb;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti0>;
coresight-ctis = <&cti0 &cti6>;
coresight-csr = <&csr>;
clocks = <&clock_aop QDSS_CLK>;

10
qcom/lahaina-gpu.dtsi
View file

@ -23,10 +23,18 @@
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&clock_gpucc GPU_CC_AHB_CLK>,
<&clock_gpucc GPU_CC_CX_GMU_CLK>,
<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&clock_gpucc GPU_CC_HUB_AON_CLK>,
<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
<&clock_aop QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"gpu_cc_cx_gmu",
"gpu_cc_hlos1_vote_gpu_smmu",
"gpu_cc_hub_aon",
"gpu_cc_hub_cx_int",
"apb_pclk";
qcom,chipid = <0x06060000>;
@ -233,7 +241,7 @@
gmu: qcom,gmu@3d69000 {
compatible = "qcom,gpu-gmu";
reg = <0x3d6a000 0x30000>,
reg = <0x3d6a000 0x34000>,
<0xb290000 0x10000>;
reg-names = "kgsl_gmu_reg",

68
qcom/lahaina-hdk.dtsi
View file

@ -1 +1,69 @@
#include "lahaina-qrd-common.dtsi"
&lahaina_snd {
qcom,model = "lahaina-hdk-snd-card";
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"Analog Mic2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"Analog Mic3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"Analog Mic4", "MIC BIAS3",
"AMIC5", "Analog Mic5",
"Analog Mic5", "MIC BIAS4",
"TX DMIC0", "Digital Mic0",
"Digital Mic0", "MIC BIAS1",
"TX DMIC1", "Digital Mic1",
"Digital Mic1", "MIC BIAS1",
"TX DMIC2", "Digital Mic2",
"Digital Mic2", "MIC BIAS3",
"TX DMIC3", "Digital Mic3",
"Digital Mic3", "MIC BIAS3",
"TX DMIC4", "Digital Mic4",
"Digital Mic4", "MIC BIAS4",
"TX DMIC5", "Digital Mic5",
"Digital Mic5", "MIC BIAS4",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5",
"Digital Mic0", "VA MIC BIAS1",
"Digital Mic1", "VA MIC BIAS1",
"Digital Mic2", "VA MIC BIAS3",
"Digital Mic3", "VA MIC BIAS3",
"Digital Mic4", "VA MIC BIAS4",
"Digital Mic5", "VA MIC BIAS4";
qcom,msm-mbhc-usbc-audio-supported = <0>;
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
};
&usb1 {
dwc3@a800000 {
dr_mode = "host";
};
};

22
qcom/lahaina-mtp.dtsi
View file

@ -79,7 +79,7 @@
st,touch-environment = "pvm";
st,trusted-touch-spi-irq = <566>;
st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>;
st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
&dsi_sw43404_amoled_fhd_plus_cmd>;
};
@ -182,13 +182,19 @@
status = "ok"
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
&q6core {
cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
};
&lahaina_snd {
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
};
&usb1 {

5
qcom/lahaina-pcie.dtsi
View file

@ -102,7 +102,7 @@
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,l1ss-sleep-disable = <0x1>;
qcom,drv-l1ss-timeout-us = <10000>;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,use-19p2mhz-aux-clk;
qcom,no-l0s-supported;
qcom,l1-2-th-scale = <2>;
@ -110,7 +110,7 @@
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <10099>;
qcom,pcie-phy-ver = <10100>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
@ -177,6 +177,7 @@
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0

19
qcom/lahaina-pm.dtsi
View file

@ -24,15 +24,28 @@
qcom,psci-mode = <0x1>;
};
CLUSTER_OFF: qcom,pm-cluster-level@1 { /* AOSS sleep */
CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */
reg = <1>;
compatible = "arm,idle-state";
idle-state-name = "l3-pc";
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x40>;
qcom,psci-mode = <0x4>;
qcom,is-reset;
qcom,min-child-idx = <1>;
};
LLCC_OFF: qcom,pm-cluster-level@2 { /* AOSS sleep */
reg = <2>;
compatible = "arm,idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
arm,psci-suspend-param = <0xc240>;
qcom,psci-mode = <0xc24>;
arm,psci-suspend-param = <0xc340>;
qcom,psci-mode = <0xc34>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <1>;

8
qcom/lahaina-pmic-overlay.dtsi
View file

@ -554,3 +554,11 @@
nvmem-cell-names = "restart_reason";
};
};
&soc {
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};
};

81
qcom/lahaina-qrd-common.dtsi
View file

@ -97,6 +97,17 @@
};
};
&q6core {
cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
};
&lahaina_snd {
qcom,model = "lahaina-qrd-snd-card";
@ -164,25 +175,8 @@
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
};
&usb1 {
status = "disabled";
};
&usb2_phy1 {
status = "disabled";
};
&usb_qmp_phy {
status = "disabled";
};
&usb2_phy0 {
qcom,param-override-seq =
<0xe6 0x6c
0x0f 0x70
0x17 0x74>;
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
};
&qupv3_se4_i2c {
@ -214,15 +208,6 @@
};
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
&battery_charger {
qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
7500000 7000000 6500000 6000000 5500000
@ -235,48 +220,6 @@
status = "ok"
};
&usb_qmp_dp_phy {
pinctrl-names = "portselect";
};
&usb0 {
ssusb_redriver = <&redriver>;
};
&qupv3_se13_i2c {
status = "ok"
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
pinctrl-names = "enable_gpio";
pinctrl-0 = <&usb3phy_portselect_gpio>;
orientation_gpio = <&tlmm 81 0>;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x6 0x4 0x4 0x6>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x2 0x1 0x1 0x2>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};
&qupv3_se15_i2c {
status = "ok"
qcom,clk-freq-out = <1000000>;

61
qcom/lahaina-qrd-module.dtsi
View file

@ -1 +1,62 @@
#include "lahaina-qrd-common.dtsi"
&usb1 {
status = "disabled";
};
&usb2_phy1 {
status = "disabled";
};
&usb_qmp_phy {
status = "disabled";
};
&usb2_phy0 {
qcom,param-override-seq =
<0xe6 0x6c
0x0f 0x70
0x17 0x74>;
};
&usb_qmp_dp_phy {
pinctrl-names = "portselect";
};
&usb0 {
ssusb_redriver = <&redriver>;
};
&qupv3_se13_i2c {
status = "ok"
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
pinctrl-names = "enable_gpio";
pinctrl-0 = <&usb3phy_portselect_gpio>;
orientation_gpio = <&tlmm 81 0>;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x6 0x4 0x4 0x6>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x2 0x1 0x1 0x2>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};

60
qcom/lahaina-qrd.dtsi
View file

@ -1,2 +1,62 @@
#include "lahaina-qrd-common.dtsi"
&usb1 {
status = "disabled";
};
&usb2_phy1 {
status = "disabled";
};
&usb_qmp_phy {
status = "disabled";
};
&usb2_phy0 {
qcom,param-override-seq =
<0xe6 0x6c
0x0c 0x70
0x17 0x74>;
};
&usb_qmp_dp_phy {
pinctrl-names = "portselect";
};
&usb0 {
ssusb_redriver = <&redriver>;
};
&qupv3_se13_i2c {
status = "ok"
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
pinctrl-names = "enable_gpio";
pinctrl-0 = <&usb3phy_portselect_gpio>;
orientation_gpio = <&tlmm 81 0>;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x6 0x4 0x4 0x6>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x2 0x1 0x1 0x2>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};

2
qcom/lahaina-regulators.dtsi
View file

@ -749,7 +749,7 @@
regulator-name = "pm8350c_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
qcom,proxy-consumer-enable;

32
qcom/lahaina-thermal-overlay.dtsi
View file

@ -50,6 +50,11 @@
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
vbat_cdsp0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
};
};
@ -69,6 +74,11 @@
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
vbat_cdsp1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
};
};
@ -79,6 +89,12 @@
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
vbat_cdsp2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
@ -99,6 +115,11 @@
trip = <&c_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
vph_cdsp0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
};
};
@ -119,6 +140,11 @@
trip = <&c_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
vph_cdsp1 {
trip = <&c_bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
};
};
@ -130,6 +156,12 @@
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
vph_cdsp2 {
trip = <&c_bcl_lvl2>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};

33
qcom/lahaina-thermal.dtsi
View file

@ -974,14 +974,13 @@
};
};
gpuss-max-step {
gpuss-0-step {
polling-delay-passive = <10>;
polling-delay = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 1>, <&tsens1 2>;
sensor-aggregation = <AGGREGATE_MAX_VALUE>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss_config: active-config0 {
gpuss0_config: active-config0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
@ -990,7 +989,29 @@
cooling-maps {
gpu_cdev {
trip = <&gpuss_config>;
trip = <&gpuss0_config>;
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
gpuss-1-step {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_config: active-config0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
gpu_cdev {
trip = <&gpuss1_config>;
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};

10
qcom/lahaina-usb.dtsi
View file

@ -29,10 +29,9 @@
<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>;
<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "core_csr_clk";
"utmi_clk", "sleep_clk";
resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
@ -365,10 +364,9 @@
<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,
<&clock_gcc GCC_USB3_SEC_CLKREF_EN>,
<&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>;
<&clock_gcc GCC_USB3_SEC_CLKREF_EN>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo", "core_csr_clk";
"utmi_clk", "sleep_clk", "xo";
resets = <&clock_gcc GCC_USB30_SEC_BCR>;
reset-names = "core_reset";

96
qcom/lahaina-v2-gpu.dtsi
View file

@ -1,7 +1,7 @@
&msm_gpu {
qcom,chipid = <0x06060001>;
qcom,initial-pwrlevel = <5>;
qcom,initial-pwrlevel = <9>;
/* Power levels */
qcom,gpu-pwrlevels {
@ -12,6 +12,38 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <840000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <778000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <738000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@ -22,10 +54,12 @@
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -36,10 +70,12 @@
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -50,10 +86,12 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882d5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -64,10 +102,26 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <9>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <491000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq-ddr7 = <8>;
qcom,bus-min-ddr7 = <6>;
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -76,12 +130,26 @@
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <6>;
qcom,bus-max-ddr8 = <9>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <379000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq-ddr7 = <8>;
qcom,bus-min-ddr7 = <6>;
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <6>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <315000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@ -91,7 +159,7 @@
qcom,bus-freq-ddr8 = <2>;
qcom,bus-min-ddr8 = <2>;
qcom,bus-max-ddr8 = <8>;
qcom,bus-max-ddr8 = <7>;
};
};
};

11
qcom/lahaina-v2.dtsi
View file

@ -43,7 +43,7 @@
};
&pcie0 {
qcom,pcie-phy-ver = <20099>;
qcom,pcie-phy-ver = <20100>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
@ -107,6 +107,7 @@
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
@ -160,7 +161,7 @@
&cpu7_l3_computemon {
qcom,core-dev-table =
< 2592000 300000000 >,
< 2035200 300000000 >,
< 2814600 1593600000 >;
};
@ -275,3 +276,9 @@
< 1881600 1 >,
< 2841600 2 >;
};
&cpu7_qoslatmon {
qcom,core-dev-table =
< 2035200 1 >,
< 2841600 2 >;
};

10
qcom/lahaina-vm-cdp.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "lahaina-vm.dtsi"
#include "lahaina-vm-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina SVM CDP";
compatible = "qcom,lahaina-cdp", "qcom,lahaina", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

1
qcom/lahaina-vm-cdp.dtsi Normal file
View file

@ -0,0 +1 @@
/*#include "display/lahaina-sde-display-cdp.dtsi"*/

0
qcom/trustedvm-ion.dtsi → qcom/lahaina-vm-ion.dtsi
View file

10
qcom/lahaina-vm-mtp.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "lahaina-vm.dtsi"
#include "lahaina-vm-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina SVM MTP";
compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp";
qcom,board-id = <0x10008 0>;
};

1
qcom/lahaina-vm-mtp.dtsi Normal file
View file

@ -0,0 +1 @@
/*#include "display/lahaina-sde-display-mtp.dtsi"*/

10
qcom/lahaina-vm-qrd.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "lahaina-vm.dtsi"
#include "lahaina-vm-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina SVM QRD";
compatible = "qcom,lahaina-qrd", "qcom,lahaina", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

1
qcom/lahaina-vm-qrd.dtsi Normal file
View file

@ -0,0 +1 @@
/*#include "display/lahaina-sde-display-qrd.dtsi"*/

102
qcom/trustedvm.dtsi → qcom/lahaina-vm.dtsi
View file

@ -6,6 +6,7 @@
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
qcom,msm-id = <415 0x10000>;
interrupt-parent = <&vgic>;
qcom-mem-buf {
@ -14,7 +15,7 @@
};
chosen {
bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8";
bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8";
linux,initrd-start = <0x2a900000>;
linux,initrd-end = <0x2b100000>; /* 8 MB */
kaslr-seed = <0xfeedbeef 0xc0def00d>;
@ -29,7 +30,8 @@
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
CPU1: cpu@100 {
@ -37,79 +39,30 @@
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU2: cpu@200 {
compatible = "arm,armv8";
reg = <0x0 0x200>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU3: cpu@300 {
compatible = "arm,armv8";
reg = <0x0 0x300>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU4: cpu@400 {
compatible = "arm,armv8";
reg = <0x0 0x400>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU5: cpu@500 {
compatible = "arm,armv8";
reg = <0x0 0x500>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU6: cpu@600 {
compatible = "arm,armv8";
reg = <0x0 0x600>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
};
CPU7: cpu@700 {
compatible = "arm,armv8";
reg = <0x0 0x700>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <0x2>;
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0x2fef7000 0x0 0x9000>;
qcom,label = <3>;
idle-states {
CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <702>;
exit-latency-us = <1061>;
min-residency-us = <4488>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
chan0_shbuf: neuron-block@0 {
no-map;
reg = <0x0 0x2ff00000 0x0 0x80000>;
qcom,label = <1>;
};
chan1_shbuf: neuron-block@1 {
no-map;
reg = <0x0 0x2ff80000 0x0 0x80000>;
qcom,label = <2>;
CLUSTER_PWR_DWN: d4 { /* C4+D4 */
compatible = "arm,idle-state";
idle-state-name = "l3-pc";
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x40000044>;
local-timer-stop;
};
};
@ -133,7 +86,6 @@
class = "message-queue";
direction = "send";
max-size = <0 65536>;
shared-buffer = <&chan0_shbuf>;
haven-label = <1>;
};
@ -143,7 +95,6 @@
class = "message-queue";
direction = "receive";
max-size = <0 65536>;
shared-buffer = <&chan1_shbuf>;
haven-label = <2>;
};
};
@ -151,7 +102,6 @@
qrtr-haven {
compatible = "qcom,qrtr-haven";
haven-label = <3>;
shared-buffer = <&qrtr_shbuf>;
};
qcom,vm-config {
@ -189,8 +139,8 @@
vcpus {
config = "/cpus";
affinity = "static";
affinity-map = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7>;
sched-priority = < (-1) >; /* relative to PVM */
affinity-map = <0x4 0x5>;
sched-priority = <0>; /* relative to PVM */
sched-timeslice = <2000>; /* in ms */
};
@ -384,7 +334,7 @@
};
};
#include "trustedvm-ion.dtsi"
#include "lahaina-vm-ion.dtsi"
#include "display/trustedvm-lahaina-sde.dtsi"
#include "display/trustedvm-lahaina-sde-display.dtsi"
#include "display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"

84
qcom/lahaina.dtsi
View file

@ -311,6 +311,11 @@
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
@ -489,7 +494,7 @@
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x2c00000>;
size = <0 0x3000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
@ -2080,6 +2085,11 @@
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
@ -2174,7 +2184,6 @@
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2186,7 +2195,6 @@
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2198,7 +2206,6 @@
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2210,7 +2217,6 @@
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2222,7 +2228,6 @@
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2234,7 +2239,6 @@
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2246,7 +2250,6 @@
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2258,7 +2261,6 @@
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
@ -2764,7 +2766,7 @@
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
<CONTROL_TCS 0>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
@ -3207,6 +3209,16 @@
qcom,iommu-dma = "bypass";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <44>;
};
qos1 {
mask = <0xf0>;
vote = <44>;
};
};
kryo-erp {
@ -3851,6 +3863,13 @@
mboxes = <&qmp_aop 0>;
};
cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
qcom,core-dev-table =
< 300000 300000000 >,
@ -3988,9 +4007,10 @@
cpu7_l3_computemon: qcom,cpu7-l3-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_latfloor>;
qcom,core-dev-table =
< 2304000 300000000 >,
< 1996800 300000000 >,
< 2400000 1516800000 >;
};
@ -4098,18 +4118,23 @@
< 300000 1 >,
< 3000000 2 >;
};
cpu7_qoslatmon: qcom,cpu7-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 1996800 1 >,
< 2400000 2 >;
};
};
wdog: qcom,wdt@17c10000{
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
<0 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};
tsens0:tsens@c222000 {
@ -4235,6 +4260,7 @@
qcom,slpi_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,net-id = <2>;
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
@ -5005,6 +5031,26 @@
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
LLCC_1: llcc_1_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x140>;
};
LLCC_2: llcc_2_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x141>;
};
LLCC_3: llcc_3_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x142>;
};
LLCC_4: llcc_4_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x143>;
};
};
qcom,ssc@5c00000 {
@ -5128,9 +5174,7 @@
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,fde-key-size;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,qsee-reentrancy-support = <2>;
@ -5397,7 +5441,7 @@
mhi,num-elements = <32>;
mhi,intmod = <0>;
mhi,msi = <1>;
mhi,priority = <1>;
mhi,priority = <0>;
mhi,brstmode = <2>;
mhi,data-type = <1>;
};

4
qcom/lahainap-v2.dtsi
View file

@ -6,10 +6,6 @@
qcom,msm-id = <439 0x20000>;
};
&pil_modem {
status = "disabled";
};
&ipa_hw {
status = "disabled";
};

4
qcom/lahainap.dtsi
View file

@ -6,10 +6,6 @@
qcom,msm-id = <439 0x10000>;
};
&pil_modem {
status = "disabled";
};
&ipa_hw {
status = "disabled";
};

6
qcom/msm-arm-smmu-holi.dtsi
View file

@ -120,10 +120,12 @@
qcom,active-only;
qcom,actlr =
/* For rt TBU +3 deep PF */
/* For rt TBU camera +3 deep PF */
<0x800 0x3ff 0x103>,
/* For nrt TBU +3 deep PF */
<0xc00 0x3ff 0x103>;
<0xc00 0x3ff 0x103>,
/* For anoc_1 TBU disable PF */
<0x0 0x3ff 0x001>;
anoc_1_tbu: anoc_1_tbu@0c705000 {
compatible = "qcom,qsmmuv500-tbu";

13
qcom/msm-arm-smmu-lahaina.dtsi
View file

@ -20,10 +20,19 @@
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&clock_gpucc GPU_CC_AHB_CLK>;
<&clock_gpucc GPU_CC_AHB_CLK>,
<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&clock_gpucc GPU_CC_CX_GMU_CLK>,
<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
<&clock_gpucc GPU_CC_HUB_AON_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
"gpu_cc_ahb",
"gpu_cc_hlos1_vote_gpu_smmu_clk",
"gpu_cc_cx_gmu_clk",
"gpu_cc_hub_cx_int_clk",
"gpu_cc_hub_aon_clk";
interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;

12
qcom/msm-arm-smmu-sdxlemur.dtsi
View file

@ -47,8 +47,8 @@
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
interconnects = <&mem_noc MASTER_APPSS_PROC
&system_noc SLAVE_IMEM_CFG>;
qcom,active-only;
periph_tbu: periph_tbu@15045000 {
@ -57,8 +57,8 @@
<0x15042200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
interconnects = <&mem_noc MASTER_APPSS_PROC
&system_noc SLAVE_IMEM_CFG>;
qcom,active-only;
};
@ -68,8 +68,8 @@
<0x15042208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
interconnects = <&mem_noc MASTER_APPSS_PROC
&system_noc SLAVE_IMEM_CFG>;
qcom,active-only;
};
};

12
qcom/msm-arm-smmu-shima.dtsi
View file

@ -20,11 +20,18 @@
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_HUB_AON_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"gpu_cc_hlos1_vote_gpu_smmu_clk";
"gpu_cc_hlos1_vote_gpu_smmu_clk",
"gpu_cc_cx_gmu_clk",
"gpu_cc_hub_cx_int_clk",
"gpu_cc_hub_aon_clk";
interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
@ -333,7 +340,6 @@
};
kgsl_iommu_coherent_test_device {
status = "disabled";
compatible = "iommu-debug-test";
iommus = <&kgsl_smmu 0x407 0>;
qcom,iommu-dma = "disabled";

6
qcom/pm6150l.dtsi
View file

@ -87,7 +87,7 @@
compatible = "qcom,adc-tm5";
reg = <0x3500>;
interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "thr-int-en";
interrupt-names = "threshold";
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
@ -283,7 +283,7 @@
pm6150l_lpg: qcom,pwms@b100 {
compatible = "qcom,pwm-lpg";
reg = <0xb100 0x300>, <0xb000 0x100>;
reg = <0xb100>, <0xb000>;
reg-names = "lpg-base", "lut-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
@ -383,7 +383,7 @@
};
&thermal_zones {
pm6150l-tz {
pm6150l_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";

227
qcom/pm7250b.dtsi
View file

@ -15,16 +15,203 @@
#address-cells = <1>;
#size-cells = <0>;
pm7250b_revid: qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100>;
};
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
};
pm7250b_charger: qcom,qpnp-smb5 {
compatible = "qcom,pm7250b-smb5";
#address-cells = <1>;
#size-cells = <0>;
#cooling-cells = <2>;
qcom,thermal-mitigation = <5400000 4500000 4000000
3500000 3000000 2500000 2000000 1500000
1000000 500000>;
qcom,chgr@1000 {
reg = <0x1000>;
interrupts =
<0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chgr-error",
"chg-state-change",
"step-chg-state-change",
"step-chg-soc-update-fail",
"step-chg-soc-update-req",
"fg-fvcal-qualified",
"vph-alarm",
"vph-drop-prechg";
};
qcom,dcdc@1100 {
reg = <0x1100>;
interrupts =
<0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "otg-fail",
"otg-oc-disable-sw",
"otg-oc-hiccup",
"bsm-active",
"high-duty-cycle",
"input-current-limiting",
"concurrent-mode-disable",
"switcher-power-ok";
};
qcom,batif@1200 {
reg = <0x1200>;
interrupts =
<0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "bat-temp",
"bat-ov",
"bat-low",
"bat-therm-or-id-missing",
"bat-terminal-missing",
"buck-oc",
"vph-ov";
};
qcom,usb@1300 {
reg = <0x1300>;
interrupts =
<0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usbin-collapse",
"usbin-vashdn",
"usbin-uv",
"usbin-ov",
"usbin-plugin",
"usbin-revi-change",
"usbin-src-change",
"usbin-icl-change";
};
qcom,dc@1400 {
reg = <0x1400>;
interrupts =
<0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x14 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dcin-vashdn",
"dcin-uv",
"dcin-ov",
"dcin-plugin",
"dcin-revi",
"dcin-pon",
"dcin-en";
};
qcom,typec@1500 {
reg = <0x1500>;
interrupts =
<0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "typec-or-rid-detect-change",
"typec-vpd-detect",
"typec-cc-state-change",
"typec-vconn-oc",
"typec-vbus-change",
"typec-attach-detach",
"typec-legacy-cable-detect",
"typec-try-snk-src-detect";
};
qcom,misc@1600 {
reg = <0x1600>;
interrupts =
<0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"smb-en",
"imp-trigger",
"temp-change",
"temp-change-smb";
};
qcom,chg-sdam@b000 {
reg = <0xb000>;
};
};
pm7250b_qg: qpnp,qg {
compatible = "qcom,pm7250b-qg";
#address-cells = <1>;
#size-cells = <0>;
qcom,vbatt-cutoff-mv = <3200>;
qcom,vbatt-low-mv = <3300>;
qcom,vbatt-low-cold-mv = <3700>;
qcom,vbatt-empty-mv = <3000>;
qcom,vbatt-empty-cold-mv = <3000>;
qcom,s3-entry-fifo-length = <2>;
qcom,qgauge@4800 {
status = "okay";
reg = <0x4800>;
interrupts =
<0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "qg-batt-missing",
"qg-vbat-low",
"qg-vbat-empty",
"qg-fifo-done",
"qg-good-ocv";
};
qcom,qg-sdam@b100 {
status = "okay";
reg = <0xb100>;
};
};
pm7250b_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
@ -161,7 +348,7 @@
compatible = "qcom,adc-tm5";
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "thr-int-en";
interrupt-names = "threshold";
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
@ -192,6 +379,32 @@
interrupt-controller;
#interrupt-cells = <2>;
};
pm7250b_pdphy: qcom,usb-pdphy@1700 {
compatible = "qcom,qpnp-pdphy";
reg = <0x1700 0x100>;
interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sig-tx",
"sig-rx",
"msg-tx",
"msg-rx",
"msg-tx-failed",
"msg-tx-discarded",
"msg-rx-discarded",
"fr-swap";
qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
<9000 3000>, /* 9V @ 3A */
<12000 2250>; /* 12V @ 2.25A */
};
};
qcom,pm7250b@3 {
@ -210,7 +423,7 @@
};
&thermal_zones {
pm7250b-tz {
pm7250b_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";

4
qcom/pm8350b.dtsi
View file

@ -251,7 +251,7 @@
trips {
ibat_lvl0:ibat-lvl0 {
temperature = <4500>;
temperature = <6000>;
hysteresis = <200>;
type = "passive";
};
@ -266,7 +266,7 @@
trips {
ibat_lvl1:ibat-lvl1 {
temperature = <5000>;
temperature = <7500>;
hysteresis = <200>;
type = "passive";
};

5
qcom/pmk8350.dtsi
View file

@ -199,6 +199,11 @@
};
};
pmk8350_sdam_5: sdam@7400 {
compatible = "qcom,spmi-sdam";
reg = <0x7400>;
};
pmk8350_sdam_13: sdam@7c00 {
compatible = "qcom,spmi-sdam";
reg = <0x7c00>;

67
qcom/pmx65.dtsi Normal file
View file

@ -0,0 +1,67 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmx65@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmx65_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmx65_pwm: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <4>;
};
pmx65_gpios: pinctrl@8800 {
compatible = "qcom,pmx65-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pmx65_temp_alarm: pmx65_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmx65_tz>;
trips {
pmx65_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmx65_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pmx65_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

1035
qcom/qg-batterydata-alium-3600mah.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

1040
qcom/qg-batterydata-atl436186020H_3780mAh.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

1041
qcom/qg-batterydata-atl466271_3300mAh.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

2
qcom/sdxlemur-cdp.dtsi
View file

@ -1,3 +1,5 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {
};

1540
qcom/sdxlemur-coresight.dtsi Normal file
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File diff suppressed because it is too large Load diff

2
qcom/sdxlemur-mtp.dtsi
View file

@ -1,3 +1,5 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {
};

117
qcom/sdxlemur-pcie.dtsi Normal file
View file

@ -0,0 +1,117 @@
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x1c00000 0x3000>,
<0x1c06000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 57 0>;
wake-gpio = <&tlmm 53 0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default
&pcie0_perst_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep
&pcie0_perst_default
&pcie0_wake_default>;
gdsc-vdd-supply = <&gcc_pcie_gdsc>;
vreg-1.8-supply = <&pmx65_l1>;
vreg-0.9-supply = <&pmx65_l4>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>;
qcom,vreg-0.9-voltage-level = <912000 912000 132000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */
interconnect-names = "icc_path";
interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
<&gcc GCC_PCIE_PIPE_CLK_SRC>,
<&gcc PCIE_PIPE_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_0_sleep_clk", "pcie_phy_refgen_clk",
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>;
resets = <&gcc GCC_PCIE_BCR>,
<&gcc GCC_PCIE_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
qcom,smmu-sid-base = <0x0200>;
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
<0x100 &apps_smmu 0x0201 0x1>;
qcom,boot-option = <0x1>;
qcom,use-19p2mhz-aux-clk;
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <0>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
};
};

54
qcom/sdxlemur-pinctrl.dtsi
View file

@ -39,5 +39,59 @@
bias-disable;
};
};
pcie0 {
pcie0_clkreq_default: pcie0_clkreq_default {
mux {
pins = "gpio56";
function = "pcie_clkreq";
};
config {
pins = "gpio56";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_perst_default: pcie0_perst_default {
mux {
pins = "gpio57";
function = "gpio";
};
config {
pins = "gpio57";
drive-strength = <2>;
bias-pull-down;
};
};
pcie0_wake_default: pcie0_wake_default {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
mux {
pins = "gpio56";
function = "gpio";
};
config {
pins = "gpio56";
drive-strength = <2>;
bias-pull-up;
};
};
};
};
};

8
qcom/sdxlemur-pmic-overlay.dtsi Normal file
View file

@ -0,0 +1,8 @@
#include "pmk8350.dtsi"
#include "pmx65.dtsi"
#include "pm7250b.dtsi"
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
};

2
qcom/sdxlemur-rumi.dtsi
View file

@ -1,3 +1,5 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {
timer {
clock-frequency = <96000>;

91
qcom/sdxlemur.dtsi
View file

@ -2,6 +2,7 @@
#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sdxlemur.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@ -15,7 +16,9 @@
qcom,msm-id = <458 0x10000>;
interrupt-parent = <&intc>;
aliases { };
aliases {
pci-domain0 = &pcie0; /* PCIe0 domain */
};
chosen { };
@ -107,6 +110,11 @@
#size-cells = <1>;
ranges;
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
intc: interrupt-controller@17800000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@ -197,6 +205,17 @@
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1100000 0x2000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x800>;
};
watchdog: qcom,wdt@17817000 {
compatible = "qcom,msm-watchdog";
reg = <0x17817000 0x1000>;
@ -294,7 +313,7 @@
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
@ -305,12 +324,26 @@
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_pipe_clk: pcie-0-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <2>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
@ -318,16 +351,16 @@
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <2>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
aopcc: clock-controller@0 {
compatible = "qcom,dummycc";
clock-output-names = "aopcc_clocks";
compatible = "qcom,aop-qmp-clk";
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
rpmhcc: clock-controller@1 {
@ -379,6 +412,10 @@
<WAKE_TCS 2>,
<CONTROL_TCS 1>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
system_pm {
compatible = "qcom,system-pm";
};
@ -408,17 +445,25 @@
system_noc: interconnect@1620000 {
compatible = "qcom,sdxlemur-system_noc";
reg = <0x1620000 0x31200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mem_noc: interconnect@9680000 {
compatible = "qcom,sdxlemur-mem_noc";
reg = <0x9680000 0x27200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect {
compatible = "qcom,sdxlemur-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos"
qcom,bcm-voters = <&apps_bcm_voter>;
};
tcsr_mutex_block: syscon@1f40000 {
@ -432,6 +477,15 @@
#hwlock-cells = <1>;
};
cache-controller@9200000 {
compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
reg = <0x9200000 0x50000>;
reg-names = "llcc_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "aopcc_closks";
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
@ -587,6 +641,28 @@
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
thermal_zones: thermal-zones {
};
};
#include "sdxlemur-pinctrl.dtsi"
@ -595,3 +671,4 @@
#include "sdxlemur-ion.dtsi"
#include "sdxlemur-usb.dtsi"
#include "sdxlemur-pm.dtsi"
#include "sdxlemur-pcie.dtsi"

20
qcom/shima-atp.dtsi
View file

@ -1 +1,21 @@
#include "shima-idp.dtsi"
&pm8008i_chip {
status = "disabled";
};
&pm8008i_ldo {
status = "disabled";
};
&pm8008j_chip {
status = "disabled";
};
&pm8008j_ldo {
status = "disabled";
};
&pm8350c_flash {
status = "disabled";
};

26
qcom/shima-audio-overlay.dtsi
View file

@ -57,7 +57,7 @@
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0x3230000 0x0>;
interrupts-extended =
<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq", "swr_wake_irq";
qcom,swr-num-ports = <3>;
@ -242,9 +242,11 @@
};
&shima_snd {
qcom,model = "shima-idp-snd-card";
qcom,model = "lahaina-shimaidp-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <0>;
qcom,wcn-bt = <1>;
qcom,tdm-max-slots = <8>;
qcom,wcd-disabled = <0>;
qcom,ext-disp-audio-rx = <0>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
@ -294,11 +296,11 @@
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS4",
"VA DMIC3", "VA MIC BIAS1",
"VA DMIC4", "VA MIC BIAS4",
"VA DMIC4", "VA MIC BIAS3",
"VA DMIC5", "VA MIC BIAS4";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
@ -308,13 +310,17 @@
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>,
<&ext_disp_audio_codec>;
<&wsa883x_0221>, <&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2",
"msm-ext-disp-audio-codec-rx";
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <2>;
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>;
qcom,cps_threshold_levels = <148 168>;
qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
qcom,cps_lower2_values = <0x0F 0x0F 0x18>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
};

12
qcom/shima-audio.dtsi
View file

@ -7,6 +7,10 @@
};
&audio_apr {
msm_audio_ion_cma: qcom,msm-audio-ion-cma {
compatible = "qcom,msm-audio-ion-cma";
};
q6core: qcom,q6core-audio {
compatible = "qcom,q6core-audio";
#address-cells = <1>;
@ -47,8 +51,10 @@
<0x00000000>, <0x00000000>,
<0x00000006>;
clock-names = "lpass_core_hw_vote";
clocks = <&lpass_core_hw_vote 0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
};
bolero: bolero-cdc {
@ -152,7 +158,7 @@
&q6core {
shima_snd: sound {
compatible = "qcom,lahaina-asoc-snd";
qcom,mi2s-audio-intf = <0>;
qcom,mi2s-audio-intf = <1>;
qcom,auxpcm-audio-intf = <1>;
qcom,wcn-bt = <0>;
qcom,ext-disp-audio-rx = <0>;

3
qcom/shima-coresight.dtsi
View file

@ -107,6 +107,7 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0_swao &cti3_swao>;
clocks = <&aopcc QDSS_CLK>;
clock-names = "apb_pclk";
@ -153,7 +154,7 @@
qcom,sw-usb;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti0>;
coresight-ctis = <&cti0 &cti3_swao>;
coresight-csr = <&csr>;
clocks = <&aopcc QDSS_CLK>;

82
qcom/shima-gpu.dtsi
View file

@ -28,13 +28,19 @@
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&aopcc QDSS_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_HUB_AON_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"apb_pclk",
"gpu_cc_hlos1_vote_gpu_smmu_clk";
"gpu_cc_hlos1_vote_gpu_smmu_clk",
"gpu_cc_cx_gmu",
"gpu_cc_hub_aon",
"gpu_cc_hub_cx_int";
qcom,chipid = <0x06060001>;
@ -135,12 +141,12 @@
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <2>;
qcom,initial-pwrlevel = <4>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <490000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <10>;
@ -153,6 +159,34 @@
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq-ddr7 = <10>;
qcom,bus-min-ddr7 = <9>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <9>;
qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq-ddr7 = <9>;
qcom,bus-min-ddr7 = <8>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <8>;
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -165,8 +199,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@ -271,24 +305,10 @@
#size-cells = <0>;
qcom,speed-bin = <158>;
qcom,initial-pwrlevel = <5>;
qcom,initial-pwrlevel = <4>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <747000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -296,13 +316,13 @@
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <10>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -315,8 +335,8 @@
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -329,8 +349,8 @@
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -343,8 +363,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

35
qcom/shima-idp.dtsi
View file

@ -2,6 +2,8 @@
#include <dt-bindings/input/input.h>
#include "shima-pmic-overlay.dtsi"
#include "display/shima-sde-display-idp.dtsi"
#include "shima-thermal-overlay.dtsi"
#include "shima-audio-overlay.dtsi"
&soc {
gpio_keys {
@ -23,6 +25,27 @@
};
};
&qupv3_se9_i2c {
status = "ok"
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 87 0x00>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
interrupt-parent = <&tlmm>;
interrupts = <87 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&sdhc_1 {
status = "ok"
@ -155,8 +178,18 @@
pinctrl-2 = <&ts_release>;
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
&dsi_r66451_amoled_video
&dsi_r66451_amoled_60hz_video>;
};
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
#include "camera/shima-camera-sensor-idp.dtsi"

81
qcom/shima-idps-digital-mics.dtsi
View file

@ -1,2 +1,83 @@
#include "shima-idp.dtsi"
&soc {
};
&shima_snd {
qcom,model = "lahaina-shimaidps-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
qcom,wcn-bt = <1>;
qcom,tdm-max-slots = <8>;
qcom,wcd-disabled = <0>;
qcom,ext-disp-audio-rx = <0>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS3",
"AMIC2", "Analog Mic2",
"Analog Mic2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"Analog Mic3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"Analog Mic4", "MIC BIAS1",
"AMIC5", "Analog Mic5",
"Analog Mic5", "MIC BIAS4",
"TX DMIC0", "Digital Mic0",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "Digital Mic1",
"TX DMIC1", "MIC BIAS3",
"TX DMIC2", "Digital Mic2",
"TX DMIC2", "MIC BIAS4",
"TX DMIC3", "Digital Mic3",
"TX DMIC3", "MIC BIAS1",
"TX DMIC4", "Digital Mic4",
"TX DMIC4", "MIC BIAS3",
"TX DMIC5", "Digital Mic5",
"TX DMIC5", "MIC BIAS4",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS1",
"VA DMIC3", "VA MIC BIAS1",
"VA DMIC4", "VA MIC BIAS4",
"VA DMIC5", "VA MIC BIAS4";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,swr-dmic-max-devs = <0>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <2>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
};

14
qcom/shima-ion.dtsi
View file

@ -16,6 +16,15 @@
qcom,ion-heap-type = "SYSTEM_SECURE";
};
qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
reg = <ION_SECURE_CARVEOUT_HEAP_ID>;
qcom,ion-heap-type = "SECURE_CARVEOUT";
cdsp {
memory-region = <&cdsp_secure_heap_mem>;
token = <0x20000000>;
};
};
qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
reg = <ION_SECURE_DISPLAY_HEAP_ID>;
memory-region = <&secure_display_memory>;
@ -39,5 +48,10 @@
memory-region = <&qseecom_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@5 { /* AUDIO ML HEAP */
reg = <ION_AUDIO_ML_HEAP_ID>;
memory-region = <&audio_cma_mem>;
qcom,ion-heap-type = "DMA";
};
};
};

3
qcom/shima-pcie.dtsi
View file

@ -62,6 +62,7 @@
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
@ -73,7 +74,7 @@
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_0_pipe_clk",
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",

60
qcom/shima-pinctrl.dtsi
View file

@ -151,6 +151,66 @@
};
};
nfc {
nfc_int_active: nfc_int_active {
/* active state */
mux {
/* GPIO 87: NFC Read Interrupt */
pins = "gpio87";
function = "gpio";
};
config {
pins = "gpio87";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_int_suspend: nfc_int_suspend {
/* sleep state */
mux {
/* GPIO 87: NFC Read Interrupt */
pins = "gpio87";
function = "gpio";
};
config {
pins = "gpio87";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_enable_active: nfc_enable_active {
mux {
/* 62: Enable,86: Firmware,63: CLOCK */
pins = "gpio62", "gpio86", "gpio63";
function = "gpio";
};
config {
pins = "gpio62", "gpio86", "gpio63";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_enable_suspend: nfc_enable_suspend {
mux {
/* 62: Enable,86: Firmware,63: CLOCK */
pins = "gpio62", "gpio86", "gpio63";
function = "gpio";
};
config {
pins = "gpio62", "gpio86", "gpio63";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
};
qupv3_se9_spi_pins: qupv3_se9_spi_pins {
qupv3_se9_spi_active: qupv3_se9_spi_active {
mux {

28
qcom/shima-pmic-overlay.dtsi
View file

@ -270,7 +270,7 @@
#size-cells = <0>;
status = "ok"
pm8008i@8 {
pm8008i_chip: pm8008i@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
@ -294,7 +294,7 @@
};
};
pm8008i@9 {
pm8008i_ldo: pm8008i@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
@ -315,7 +315,7 @@
L1I: pm8008i_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8008i_l1";
regulator-min-microvolt = <1000000>;
regulator-min-microvolt = <224000>;
regulator-max-microvolt = <1200000>;
qcom,min-dropout-voltage = <225000>;
qcom,hpm-min-load = <30000>;
@ -324,7 +324,7 @@
L2I: pm8008i_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8008i_l2";
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <264000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <184000>;
qcom,hpm-min-load = <30000>;
@ -349,7 +349,7 @@
L5I: pm8008i_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8008i_l5";
regulator-min-microvolt = <1700000>;
regulator-min-microvolt = <1544000>;
regulator-max-microvolt = <1900000>;
qcom,min-dropout-voltage = <152000>;
};
@ -372,7 +372,7 @@
};
};
pm8008j@c {
pm8008j_chip: pm8008j@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
@ -396,7 +396,7 @@
};
};
pm8008j@d {
pm8008j_ldo: pm8008j@d {
compatible = "qcom,i2c-pmic";
reg = <0xd>;
#address-cells = <1>;
@ -417,7 +417,7 @@
L1J: pm8008j_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8008j_l1";
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <288000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <160000>;
qcom,hpm-min-load = <30000>;
@ -426,7 +426,7 @@
L2J: pm8008j_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8008j_l2";
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <448000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <0>;
qcom,hpm-min-load = <30000>;
@ -435,7 +435,7 @@
L3J: pm8008j_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8008j_l3";
regulator-min-microvolt = <1650000>;
regulator-min-microvolt = <1592000>;
regulator-max-microvolt = <1950000>;
qcom,min-dropout-voltage = <56000>;
};
@ -501,3 +501,11 @@
io-channels = <&pmk8350_vadc PMR735B_ADC7_DIE_TEMP>;
io-channel-names = "thermal";
};
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
};

125
qcom/shima-qrd.dtsi
View file

@ -1,6 +1,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "shima-pmic-overlay.dtsi"
#include "shima-thermal-overlay.dtsi"
#include "shima-audio-overlay.dtsi"
#include "display/shima-sde-display-qrd.dtsi"
&soc {
gpio_keys {
@ -22,6 +25,27 @@
};
};
&qupv3_se9_i2c {
status = "ok"
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 87 0x00>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
interrupt-parent = <&tlmm>;
interrupts = <87 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&sdhc_1 {
status = "ok"
@ -166,3 +190,104 @@
5000000 4500000 4000000 3500000 3000000
2500000 2000000 1500000 1000000 500000>;
};
&qupv3_se10_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok"
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <23 0x2008>;
focaltech,reset-gpio = <&tlmm 22 0x00>;
focaltech,irq-gpio = <&tlmm 23 0x2008>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
vdd-supply = <&L3C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
};
};
&shima_snd {
qcom,model = "lahaina-shimaqrd-snd-card";
qcom,audio-routing =
"TX DMIC0", "Digital Mic0",
"Digital Mic0", "MIC BIAS1",
"TX DMIC1", "Digital Mic1",
"Digital Mic1", "MIC BIAS1",
"TX DMIC2", "Digital Mic2",
"Digital Mic2", "MIC BIAS3",
"TX DMIC3", "Digital Mic3",
"Digital Mic3", "MIC BIAS3",
"TX DMIC4", "Digital Mic4",
"Digital Mic4", "MIC BIAS4",
"TX DMIC5", "Digital Mic5",
"Digital Mic5", "MIC BIAS4",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5";
qcom,swr-dmic-max-devs = <0>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <1>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
};
&dai_mi2s2 {
qcom,msm-mi2s-tx-lines = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};

34
qcom/shima-qupv3.dtsi
View file

@ -60,6 +60,23 @@
status = "ok"
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@994000 {
compatible = "qcom,msm-geni-console";
reg = <0x994000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok"
};
qupv3_se8_i2c: i2c@980000 {
compatible = "qcom,i2c-geni";
reg = <0x980000 0x4000>;
@ -270,23 +287,6 @@
status = "disabled";
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@994000 {
compatible = "qcom,msm-geni-console";
reg = <0x994000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok"
};
qupv3_se14_i2c: i2c@998000 {
compatible = "qcom,i2c-geni";
reg = <0x998000 0x4000>;

74
qcom/shima-regulators.dtsi
View file

@ -150,9 +150,9 @@
pm8350_s9: regulator-pm8350-s9 {
regulator-name = "pm8350_s9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <950000>;
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1500000>;
qcom,init-voltage = <950000>;
qcom,init-voltage = <952000>;
};
};
@ -165,7 +165,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2040000>;
qcom,init-voltage = <1200000>;
qcom,init-voltage = <1800000>;
};
};
@ -178,7 +178,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2040000>;
qcom,init-voltage = <1700000>;
qcom,init-voltage = <1880000>;
};
};
@ -191,7 +191,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <382000>;
regulator-max-microvolt = <1654000>;
qcom,init-voltage = <382000>;
qcom,init-voltage = <1256000>;
};
};
@ -209,7 +209,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
qcom,init-voltage = <825000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -228,7 +228,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-voltage = <3072000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -247,7 +247,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <470000>;
regulator-max-microvolt = <910000>;
qcom,init-voltage = <470000>;
qcom,init-voltage = <504000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -299,7 +299,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
qcom,init-voltage = <1140000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -318,7 +318,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2400000>;
qcom,init-voltage = <2952000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -337,7 +337,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
qcom,init-voltage = <870000>;
qcom,init-voltage = <904000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -357,7 +357,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1080000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -412,7 +412,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
qcom,init-voltage = <3008000>;
qcom,init-voltage = <3296000>;
};
};
@ -430,9 +430,28 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1620000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
L1C_AO: pm8350c_l1_ao: regulator-pm8350c-l1-ao {
regulator-name = "pm8350c_l1_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
};
L1C_SO: pm8350c_l1_so: regulator-pm8350c-l1-so {
regulator-name = "pm8350c_l1_so";
qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
qcom,init-enable = <0>;
};
};
rpmh-regulator-ldoc2 {
@ -525,7 +544,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <1650000>;
qcom,init-voltage = <2960000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -582,7 +601,7 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-voltage = <2960000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
@ -601,9 +620,30 @@
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
qcom,init-voltage = <720000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
L10C_AO:
pm8350c_l10_ao: regulator-pm8350c-l10-ao {
regulator-name = "pm8350c_l10_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
};
L10C_SO:
pm8350c_l10_so: regulator-pm8350c-l10-so {
regulator-name = "pm8350c_l10_so";
qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
qcom,init-enable = <0>;
};
};
rpmh-regulator-ldoc11 {

254
qcom/shima-thermal-overlay.dtsi Normal file
View file

@ -0,0 +1,254 @@
#include <dt-bindings/thermal/thermal_qti.h>
&mdss_mdp {
#cooling-cells = <2>;
};
&battery_charger {
#cooling-cells = <2>;
};
&thermal_zones {
socd {
cooling-maps {
socd_cpu4 {
trip = <&socd_trip>;
cooling-device = <&cpu4_isolate 1 1>;
};
socd_cpu5 {
trip = <&socd_trip>;
cooling-device = <&cpu5_isolate 1 1>;
};
socd_cpu6 {
trip = <&socd_trip>;
cooling-device = <&cpu6_isolate 1 1>;
};
socd_cpu7 {
trip = <&socd_trip>;
cooling-device = <&cpu7_isolate 1 1>;
};
};
};
pm8350b-bcl-lvl0 {
cooling-maps {
vbat_cpu4 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu4_isolate 1 1>;
};
vbat_cpu5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_isolate 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm8350b-bcl-lvl1 {
cooling-maps {
vbat_cpu6 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu6_isolate 1 1>;
};
vbat_cpu7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu7_isolate 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8350b-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
pm8350c-bcl-lvl0 {
disable-thermal-zone;
cooling-maps {
vph_cpu4 {
trip = <&c_bcl_lvl0>;
cooling-device = <&cpu4_isolate 1 1>;
};
vph_cpu5 {
trip = <&c_bcl_lvl0>;
cooling-device = <&cpu5_isolate 1 1>;
};
vph_gpu0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm8350c-bcl-lvl1 {
disable-thermal-zone;
cooling-maps {
vph_cpu6 {
trip = <&c_bcl_lvl1>;
cooling-device = <&cpu6_isolate 1 1>;
};
vph_cpu7 {
trip = <&c_bcl_lvl1>;
cooling-device = <&cpu7_isolate 1 1>;
};
vph_gpu1 {
trip = <&c_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8350c-bcl-lvl2 {
disable-thermal-zone;
cooling-maps {
vph_gpu2 {
trip = <&c_bcl_lvl2>;
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
pm8350b_tz {
cooling-maps {
battery_cdev {
trip = <&pm8350b_trip0>;
cooling-device = <&battery_charger
THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
pm8350_tz {
cooling-maps {
pm8350_gpu {
trip = <&pm8350_trip0>;
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pm8350_cpu0_freq {
trip = <&pm8350_trip0>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pm8350_cpu1 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu1_isolate 1 1>;
};
pm8350_cpu2 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu2_isolate 1 1>;
};
pm8350_cpu3 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu3_isolate 1 1>;
};
pm8350_cpu4 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu4_isolate 1 1>;
};
pm8350_cpu5 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu5_isolate 1 1>;
};
pm8350_cpu6 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu6_isolate 1 1>;
};
pm8350_cpu7 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu7_isolate 1 1>;
};
};
};
pm8350c_tz {
cooling-maps {
pm8350c_mdm {
trip = <&pm8350c_trip0>;
cooling-device = <&modem_tj THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pm8350c_nsp {
trip = <&pm8350c_trip0>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
pmr735b_tz {
cooling-maps {
pmr735b_pa {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_pa_dsc
THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pmr735b_pa_fr1 {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_pa_fr1_dsc
THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pmr735b_mmw0 {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_mmw0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pmr735b_mmw1 {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_mmw1 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pmr735b_mmw2 {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_mmw2 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pmr735b_mmw3 {
trip = <&pmr735b_trip0>;
cooling-device = <&modem_mmw3 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
};
};
};

265
qcom/shima-thermal.dtsi
View file

@ -60,6 +60,18 @@
#cooling-cells = <2>;
};
};
qcom,cpu-voltage-cdev {
compatible = "qcom,cc-cooling-devices";
apc1_cluster: qcom,apc1-cluster {
qcom,cpus = <&CPU4 &CPU7>;
#cooling-cells = <2>;
};
};
};
&msm_gpu {
#cooling-cells = <2>;
};
&thermal_zones {
@ -643,99 +655,6 @@
};
};
nspss-0-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
thermal-governor = "step_wise";
trips {
nspss0_trip0: nspss0-trip0 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev {
trip = <&nspss0_trip0>;
cooling-device = <&cdsp_sw 3 3>;
};
modem-pa-cdev {
trip = <&nspss0_trip0>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss0_trip0>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-1-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
thermal-governor = "step_wise";
trips {
nspss1_trip0: nspss1-trip0 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev {
trip = <&nspss1_trip0>;
cooling-device = <&cdsp_sw 3 3>;
};
modem-pa-cdev {
trip = <&nspss1_trip0>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss1_trip0>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-2-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
thermal-governor = "step_wise";
trips {
nspss2_trip0: nspss2-trip0 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev {
trip = <&nspss2_trip0>;
cooling-device = <&cdsp_sw 3 3>;
};
modem-pa-cdev {
trip = <&nspss2_trip0>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss2_trip0>;
cooling-device = <&modem_tj 3 3>;
};
};
};
cpu-0-0-step {
polling-delay-passive = <0>;
polling-delay = <0>;
@ -1033,10 +952,168 @@
trips {
gpuss_config: active-config0 {
temperature = <95000>;
hysteresis = <20000>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
gpu_cdev {
trip = <&gpuss_config>;
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
nspss-0-step {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 3>;
trips {
nspss0_trip0: nspss0-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss0_trip1: nspss0-trip1 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss0_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss0_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
gpu_cdev {
trip = <&nspss0_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
};
modem-pa-cdev {
trip = <&nspss0_trip1>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss0_trip1>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-1-step {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 4>;
trips {
nspss1_trip0: nspss1-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss1_trip1: nspss1-trip1 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss1_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss1_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
gpu_cdev {
trip = <&nspss1_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
};
modem-pa-cdev {
trip = <&nspss1_trip1>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss1_trip1>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-2-step {
polling-delay-passive = <10>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 5>;
trips {
nspss2_trip0: nspss2-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss2_trip1: nspss2-trip1 {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss2_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss2_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
gpu_cdev {
trip = <&nspss2_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
};
modem-pa-cdev {
trip = <&nspss2_trip1>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss2_trip1>;
cooling-device = <&modem_tj 3 3>;
};
};
};
};

10
qcom/shima-vm-atp.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "shima-vm.dtsi"
#include "shima-vm-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima VM ATP";
compatible = "qcom,shima-atp", "qcom,shima", "qcom,atp";
qcom,board-id = <0x10021 0>;
};

2
qcom/shima-vm-atp.dtsi Normal file
View file

@ -0,0 +1,2 @@
&soc {
};

10
qcom/shima-vm-idp.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "shima-vm.dtsi"
#include "shima-vm-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima VM IDP";
compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp";
qcom,board-id = <34 0>;
};

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