Merge "dt-bindings: interconnect: add OSM L3 bindings"

bindings/clock/qcom,camcc.txt

@@ -7,6 +7,11 @@ Required properties :
 			"qcom,lahaina-camcc"
 			"qcom,lahaina-camcc-v2"
 			"qcom,shima-camcc"
+			"qcom,sm8150-camcc"
+			"qcom,sm8150-camcc-v2"
+			"qcom,sa8155-camcc"
+			"qcom,sa8155-camcc-v2"
+
 - reg : shall contain base register location and length.
 - reg-names: names of registers listed in the same order as in
 		the reg property.

bindings/clock/qcom,debugcc.txt

@@ -8,6 +8,7 @@ Required properties :
 			"qcom,shima-debugcc"
 			"qcom,holi-debugcc"
 			"qcom,sdxlemur-debugcc"
+			"qcom,sm8150-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.

bindings/clock/qcom,dispcc.txt

@@ -9,6 +9,8 @@ Required properties :
 			"qcom,lahaina-dispcc"
 			"qcom,shima-dispcc"
 			"qcom,holi-dispcc"
+			"qcom,sm8150-dispcc"
+			"qcom,sm8150-dispcc-v2"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.

bindings/clock/qcom,gcc.txt

@@ -24,10 +24,10 @@ Required properties :
 			"qcom,gcc-sdm660"
 			"qcom,gcc-sdm845"
 			"qcom,lahaina-gcc"
-			"qcom,gcc-sm8150"
-			"qcom,gcc-sm8150-v2"
-			"qcom,gcc-sa8155"
-			"qcom,gcc-sa8155-v2"
+			"qcom,sm8150-gcc"
+			"qcom,sm8150-gcc-v2"
+			"qcom,sa8155-gcc"
+			"qcom,sa8155-gcc-v2"
 			"qcom,shima-gcc"
 			"qcom,holi-gcc"
 			"qcom,sdxlemur-gcc"

bindings/clock/qcom,gpucc.txt

@@ -5,7 +5,10 @@ Required properties :
 - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
 		"qcom,lahaina-gpucc",
 		"qcom,shima-gpucc",
-		"qcom,holi-gpucc".
+		"qcom,holi-gpucc",
+		"qcom,sm8150-gpucc",
+		"qcom,sa8155-gpucc".
+
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
 		Must contain "cc_base".

bindings/clock/qcom,npucc.txt

@@ -0,0 +1,33 @@
+Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding
+----------------------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,sm8150-npucc"
+			"qcom,sm8150-npucc-v2"
+			"qcom,sa8155-npucc"
+			"qcom,sa8155-npucc-v2"
+
+- reg : shall contain base register location and length.
+- reg-names: names of registers listed in the same order as in
+	     the reg property.
+- vdd_cx-supply: phandle to the CX rail that needs to be voted
+		 on behalf of the NPU CC clocks.
+- vdd_gdsc-supply: phandle to the NPU core GDSC that needs to be
+		   toggled as part of the CRC sequence.
+- #clock-cells : shall contain 1.
+- #reset-cells : shall contain 1.
+
+Optional properties :
+- #power-domain-cells : from generic power domain binding, shall contain 1
+
+Example:
+	npucc: qcom,npucc {
+		compatible = "qcom,npucc-sm8150";
+		reg = <0x9910000 0x10000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&pm8150l_s6_level>;
+		vdd_gdsc-supply = <&npu_core_gdsc>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};

bindings/clock/qcom,scc.txt

@@ -0,0 +1,23 @@
+Qualcomm Technologies, Inc. Sensor Clock Controller Bindings
+
+Required properties:
+- compatible : shall contain only one of the following:
+			"qcom,sm8150-scc"
+			"qcom,sm8150-scc-v2"
+			"qcom,sa8155-scc"
+			"qcom,sa8155-scc-v2"
+
+- reg: shall contain base register location and length.
+- vdd_scc_cx-supply: the logic rail supply.
+- #clock-cells: shall contain 1.
+
+Optional properties :
+- #power-domain-cells : from generic power domain binding, shall contain 1
+
+Example:
+	qcom,scc@2b10000 {
+		compatible = "qcom,scc-sm8150";
+		reg = <0x2b10000 0x30000>;
+		vdd_scc_cx-supply = <&VDD_CX_LEVEL>;
+		#clock-cells = <1>;
+	};

bindings/clock/qcom,videocc.txt

@@ -7,6 +7,10 @@ Required properties :
 			"qcom,sdm845-videocc"
 			"qcom,lahaina-videocc"
 			"qcom,shima-videocc"
+			"qcom,sm8150-videocc"
+			"qcom,sm8150-videocc-v2"
+			"qcom,sa8155-videocc"
+			"qcom,sa8155-videocc-v2"
 
 - reg : shall contain base register location and length
 - #clock-cells : from common clock binding, shall contain 1.

bindings/interconnect/qcom,osm-l3.txt

@@ -0,0 +1,25 @@
+Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding
+-----------------------------------------------------------
+
+The EPSS L3 Interconnect provider supports the scaling of L3 cache
+performance states of the CPU subsystem.
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,sdm845-osm-l3",
+			"qcom,sm8150-osm-l3";
+- reg : Address and length of the register set for the device
+- clock-names: should contain "xo", "alternate"
+- clocks: list of phandle and clock specifier pairs corresponding to
+          entries in the clock-names property.
+- #interconnect-cells : should contain 1
+
+Examples:
+
+osm_l3: interconnect@0x18321000 {
+	reg = <0x18321000 0x1400>;
+	compatible = "qcom,sm8150-osm-l3";
+	clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+	clock-names = "xo", "alternate";
+	#interconnect-cells = <1>;
+};

bindings/interconnect/qcom,sm8150.txt

@@ -21,9 +21,6 @@ Required properties :
 			"qcom,sm8150-mc_virt";
 			"qcom,sm8150-mmss_noc";
 			"qcom,sm8150-system_noc";
-			"qcom,sm8150-gem_noc_display";
-			"qcom,sm8150-mc_virt_display";
-			"qcom,sm8150-mmss_noc_display";
 - #interconnect-cells : should contain 1
 
 Examples:

bindings/ufs/ufs-qcom.txt

@@ -16,6 +16,8 @@ Required properties:
 			 for sdm845 emulation,
 			"qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy
 			 present on Lahaina chipset.
+			"qcom,ufs-phy-qmp-v4" for V4 ufs phy present
+			 on SM8150 chipset.
 			"qcom,ufs-phy-qmp-v3" for V3 ufs phy
 			 present on holi chipset.
 - reg               : should contain PHY register address space (mandatory),