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Merge "phy: ufs: Add UFS PHY support for Holi"
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commit
a5bfd60250
2 changed files with 13 additions and 4 deletions
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@ -89,6 +89,12 @@ config PHY_QCOM_UFS_QRBTC_SDM845
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No low power mode support is present.
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Doesn't restrict number of lanes.
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config PHY_QCOM_UFS_V3
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tristate
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default PHY_QCOM_UFS
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help
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Support for 8nm UFS QMP phy present on QCOM chipsets.
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endif
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config PHY_QCOM_USB_HS
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@ -50,17 +50,20 @@ static int ufs_qcom_phy_qmp_v3_phy_calibrate(struct phy *generic_phy)
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phy_cal_table_2nd_lane,
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ARRAY_SIZE(phy_cal_table_2nd_lane));
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} else {
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_no_g4,
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ARRAY_SIZE(phy_cal_table_rate_A_no_g4));
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
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ARRAY_SIZE(phy_cal_table_rate_A));
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if (ufs_qcom_phy->lanes_per_direction == 2)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane_no_g4,
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ARRAY_SIZE(phy_cal_table_2nd_lane_no_g4));
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phy_cal_table_2nd_lane,
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ARRAY_SIZE(phy_cal_table_2nd_lane));
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}
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if (is_rate_B)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
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ARRAY_SIZE(phy_cal_table_rate_B));
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/* flush buffered writes */
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mb();
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err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
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