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ARM: dts: msm: Add edac node for Lahaina SoC

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Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.

Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432
This commit is contained in:
Murali Nalajala 2019-07-29 14:09:08 -07:00
commit aa872263c7
1 changed files with 7 additions and 0 deletions
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7
qcom/lahaina.dtsi
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@ -612,6 +612,13 @@
status = "disabled";
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
};
};
#include "lahaina-pinctrl.dtsi"