mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
ARM: dts: msm: Add USB PHY devices and related resources on Lahaina
This change adds USB PHYs device node and related required resources for USB ports on Lahaina. Change-Id: I20a838fe555c776d4a5336ac9bef9cd15ac5f11d
This commit is contained in:
Mayank Rana
parent
5c07efb816
commit
ad5cf39cb5
2 changed files with 245 additions and 1 deletions
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@ -66,6 +66,18 @@
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};
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};
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&usb2_phy0 {
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status = "disabled";
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};
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&usb2_phy1 {
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status = "disabled";
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};
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&usb_qmp_dp_phy {
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status = "disabled";
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};
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&usb0 {
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/delete-property/ extcon;
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dwc3@a600000 {
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@ -1,3 +1,6 @@
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#include <dt-bindings/clock/qcom,gcc-lahaina.h>
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#include <dt-bindings/phy/qcom,lahaina-qmp-usb3.h>
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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@ -48,6 +51,7 @@
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compatible = "snps,dwc3";
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reg = <0xa600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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@ -92,6 +96,214 @@
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e3000 0x114>,
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<0x088e2000 0x4>;
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reg-names = "hsusb_phy_base",
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"eud_enable_reg";
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vdd-supply = <&pm8350_l5>;
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vdda18-supply = <&pm8350c_l1>;
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vdda33-supply = <&pm8350_l2>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* Primary USB port related QMP USB DP Combo PHY */
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm8350_l1>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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qcom,vdd-max-load-uA = <47000>;
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core-supply = <&pm8350_l6>;
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clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
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<&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
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"pipe_clk_ext_src", "ref_clk_src",
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"com_aux_clk";
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resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&clock_gcc GCC_USB3PHY_PHY_PRIM_BCR>;
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reset-names = "global_phy_reset", "phy_reset";
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qcom,qmp-phy-reg-offset =
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<USB3_DP_PCS_PCS_STATUS1
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USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
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USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
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USB3_DP_PCS_POWER_DOWN_CONTROL
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USB3_DP_PCS_SW_RESET
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USB3_DP_PCS_START_CONTROL
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0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
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USB3_DP_COM_POWER_DOWN_CTRL
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USB3_DP_COM_SW_RESET
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USB3_DP_COM_RESET_OVRD_CTRL
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USB3_DP_COM_PHY_MODE_CTRL
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USB3_DP_COM_TYPEC_CTRL
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USB3_DP_PCS_CLAMP_ENABLE>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x0a 0
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USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
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USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
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USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
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USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
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USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
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USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
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USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
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USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
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USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
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USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
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USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
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USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
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USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
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USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
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USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0
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USB3_DP_QSERDES_TXA_LANE_MODE_1 0x55 0
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USB3_DP_QSERDES_TXA_LANE_MODE_4 0x2A 0
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USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
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USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
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USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0
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USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
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USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
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USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x08 0
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
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USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
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USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
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USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
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USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBF 0
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF 0
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3F 0
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x94 0
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USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
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USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
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USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x00 0
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USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
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USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
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USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
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USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0
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USB3_DP_QSERDES_TXB_LANE_MODE_1 0x55 0
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USB3_DP_QSERDES_TXB_LANE_MODE_4 0x2A 0
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USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
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USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
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USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x02 0
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USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
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USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
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USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x08 0
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
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USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
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USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
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USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
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USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF 0
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF 0
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x94 0
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USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
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USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
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USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x00 0
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USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
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USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
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USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
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USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
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USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
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USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
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USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
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USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
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USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
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USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
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USB3_DP_PCS_CDR_RESET_TIME 0x0F 0
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USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
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USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
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USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
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USB3_DP_PCS_EQ_CONFIG1 0x4B 0
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USB3_DP_PCS_EQ_CONFIG5 0x10 0
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USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
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USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
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0xffffffff 0xffffffff 0x00>;
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};
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usb1: ssusb@a800000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa800000 0x100000>;
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@ -142,6 +354,7 @@
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compatible = "snps,dwc3";
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reg = <0xa800000 0xcd00>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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@ -152,11 +365,30 @@
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snps,dis_enblslpm_quirk;
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usb-core-id = <1>;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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maximum-speed = "high-speed";
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dr_mode = "drd";
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};
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};
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/* Secondary USB port related High Speed PHY */
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usb2_phy1: hsphy@88e4000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e4000 0x114>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&pm8350_l5>;
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vdda18-supply = <&pm8350c_l1>;
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vdda33-supply = <&pm8350_l2>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>;
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reset-names = "phy_reset";
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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