A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: add trusted vm dtsi files for shima target"

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qctecmdr 2020-09-07 23:34:13 -07:00 • committed by Gerrit - the friendly Code Review server
commit aee9bc7e18
1 changed files with 68 additions and 0 deletions
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68
display/trustedvm-shima-sde.dtsi Normal file
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#include "shima-sde-common.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
};
&mdss_mdp {
reg = <0xae00000 0x84208>,
<0xaeb0000 0x2008>,
<0xaeac000 0x214>,
<0xaf50000 0x038>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"swfuse_phys";
qcom,sde-hw-version = <0x60070000>;
clocks =
<&clock_cpucc GCC_DISP_AHB_CLK>,
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk";
qcom,sde-trusted-vm-env;
qcom,vram-size = <0x200000>;
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi1 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};
&mdss_dsi_phy1 {
qcom,dsi-pll-in-trusted-vm;
};