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msm: camera: isp: Write zero to clear register after global clear command

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Clear registers hold the programmed values unless explicitly set to zero.
This can cause problems in cases where a global clear is issued which
encompasses the registers for which clear mask was set in a different
instance of IRQ controller. We should not wait for the next IRQ to clear
the undesired bits in clear register. This change makes sure that the
actions of a particular IRQ controller do not affect the other. Write
zeros explicitly to clear registers corresponding to status registers
after global clear is issued in IRQ handler.

CRs-Fixed: 2775499
Change-Id: Ic57302e5862d9453a94c4e8f470215dacb8978ec
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
This commit is contained in:
Mukund Madhusudan Atre 2020-09-21 14:33:26 -07:00 • committed by Gerrit - the friendly Code Review server
commit afa957e59e
1 changed files with 14 additions and 5 deletions
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19
drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
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@ -722,19 +722,28 @@ irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv)
if (irq_register->top_half_enable_mask[j] &
controller->irq_status_arr[i])
need_th_processing[j] = true;
CAM_DBG(CAM_IRQ_CTRL,
"i %d j %d need_th_processing = %d",
i, j, need_th_processing[j]);
CAM_DBG(CAM_IRQ_CTRL,
"i %d j %d need_th_processing = %d",
i, j, need_th_processing[j]);
}
}
CAM_DBG(CAM_IRQ_CTRL, "Status Registers read Successful");
if (controller->global_clear_offset)
if (controller->global_clear_offset) {
cam_io_w_mb(controller->global_clear_bitmask,
controller->mem_base + controller->global_clear_offset);
for (i = 0; i < controller->num_registers; i++) {
irq_register = &controller->irq_register_arr[i];
if (controller->irq_status_arr[i])
cam_io_w_mb(0x0, controller->mem_base +
irq_register->clear_reg_offset);
}
CAM_DBG(CAM_IRQ_CTRL, "Status Clear done");
CAM_DBG(CAM_IRQ_CTRL, "Global Clear done from %s",
controller->name);
}
for (i = 0; i < CAM_IRQ_PRIORITY_MAX; i++) {
if (need_th_processing[i]) {