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| Filename | Latest commit message | Latest commit date |
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afa957e59e
Clear registers hold the programmed values unless explicitly set to zero. This can cause problems in cases where a global clear is issued which encompasses the registers for which clear mask was set in a different instance of IRQ controller. We should not wait for the next IRQ to clear the undesired bits in clear register. This change makes sure that the actions of a particular IRQ controller do not affect the other. Write zeros explicitly to clear registers corresponding to status registers after global clear is issued in IRQ handler. CRs-Fixed: 2775499 Change-Id: Ic57302e5862d9453a94c4e8f470215dacb8978ec Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org> |
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