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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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fw-api: CL 32023116 - update fw common interface files
Change-Id: I41fd396e1c21471630e06770d2183b237cdc91ae CRs-Fixed: 3830439
This commit is contained in:
spuligil
parent
ca1e7dffba
commit
b2bc33ab7f
1 changed files with 166 additions and 1 deletions
167
fw/htt.h
167
fw/htt.h
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@ -282,9 +282,10 @@
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* 3.152 Add decap_type in htt_rx_peer_metadata_v1b.
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* 3.153 Add passthru_pkt flag in rx_peer_metadata structs.
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* 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def.
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* 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 154
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#define HTT_CURRENT_VERSION_MINOR 155
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -6197,6 +6198,11 @@ enum htt_srng_ring_id {
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* dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for
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* full pkt buffer each mode ctrl/data type/subtype for
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* fpmo mode
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* dword29- b'0-31 - rdi_based_source_cfg
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* Each bit maps to an RDI; if set, the corresponding
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* ring ID is configured as a source buffer.
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* Applies only to HTT_RXDMA_WBM_BUF0/1/2_RING.
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* dword30- b'0-31 - wifi8 header length configurations.
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*/
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PREPACK struct htt_rx_ring_selection_cfg_t {
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A_UINT32 msg_type: 8,
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@ -6280,6 +6286,21 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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* Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING
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*/
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A_UINT32 rdi_based_source_cfg;
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A_UINT32 rxmon_fpmo_data_hdrlen : 2,
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rxmon_fpmo_ctrl_hdrlen : 2,
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rxmon_fpmo_mgmt_hdrlen : 2,
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rxmon_fp_data_hdrlen : 2,
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rxmon_fp_ctrl_hdrlen : 2,
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rxmon_fp_mgmt_hdrlen : 2,
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rxmon_mo_data_hdrlen : 2,
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rxmon_mo_ctrl_hdrlen : 2,
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rxmon_mo_mgmt_hdrlen : 2,
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rxmon_md_data_hdrlen : 2,
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rxmon_md_ctrl_hdrlen : 2,
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rxmon_md_mgmt_hdrlen : 2,
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rxmon_enable_hdr_per_ppdu : 1,
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rxmon_rsvd : 7;
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} POSTPACK;
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/**
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@ -6963,6 +6984,150 @@ enum htt_reg_write_selection {
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M 0x00000003
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S 0
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M 0x0000000C
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S 2
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M 0x00000030
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S 4
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M 0x000000C0
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S 6
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M 0x00000300
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S 8
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M 0x00000C00
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S 10
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M 0x00003000
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S 12
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M 0x0000C000
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S 14
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M 0x00030000
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S 16
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M 0x000C0000
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S 18
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M 0x00300000
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S 20
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M 0x00C00000
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S 22
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M 0x01000000
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S 24
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)
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#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)); \
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} while (0)
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/*
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* Subtype based MGMT frames enable bits.
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* FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other
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