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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add UFS support for SA6155
Add UFS host controller and UFS PHY (attached to embedded UFS card) for SA6155 platform. Change-Id: Ic75617e3d8eb406f876cc71c8931bcfee545438d
This commit is contained in:
Veera Vegivada
parent
844bcc5e6b
commit
b433f97c83
3 changed files with 174 additions and 0 deletions
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@ -1 +1,29 @@
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#include "sa6155-adp-common.dtsi"
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v3-660";
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vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
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vdda-pll-supply = <&pm6155_1_l12>;
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vdda-phy-max-microamp = <30000>;
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vdda-pll-max-microamp = <12000>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm6155_1_l17>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm6155_1_s4>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <600000>;
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qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vddp-ref-clk-min-uV = <1232000>;
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qcom,vddp-ref-clk-max-uV = <1260000>;
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status = "ok"
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};
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@ -1 +1,29 @@
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#include "sa6155-adp-common.dtsi"
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v3-660";
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vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
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vdda-pll-supply = <&pm6155_1_l12>;
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vdda-phy-max-microamp = <30000>;
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vdda-pll-max-microamp = <12000>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm6155_1_l17>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm6155_1_s4>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <600000>;
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qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vddp-ref-clk-min-uV = <1232000>;
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qcom,vddp-ref-clk-max-uV = <1260000>;
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status = "ok"
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};
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118
qcom/sm6150.dtsi
118
qcom/sm6150.dtsi
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@ -7,6 +7,7 @@
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,scc-sm6150.h>
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#include <dt-bindings/clock/qcom,videocc-sm6150.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sm6150.h>
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@ -24,6 +25,7 @@
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se0_2uart;
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};
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@ -1045,6 +1047,122 @@
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#interconnect-cells = <1>;
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};
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ufsphy_mem: ufsphy_mem@1d87000 {
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reg = <0x1d87000 0xe00>; /* PHY regs */
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reg-names = "phy_mem";
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#phy-cells = <0>;
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lanes-per-direction = <1>;
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clock-names = "ref_clk_src",
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"ref_clk",
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"ref_aux_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_MEM_CLKREF_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufshc_mem 0>;
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status = "disabled";
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};
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ufshc_mem: ufshc@1d84000 {
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compatible = "qcom,ufshc";
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reg = <0x1d84000 0x3000>,
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<0x1d90000 0x8000>;
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reg-names = "ufs_mem", "ufs_ice";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy_mem>;
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phy-names = "ufsphy";
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#reset-cells = <1>;
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lanes-per-direction = <1>;
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limit-phy-submode = <0>;
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dev-ref-clk-freq = <0>; /* 19.2 MHz */
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spm-level = <5>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
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freq-table-hz =
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<50000000 200000000>,
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<0 0>,
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<0 0>,
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<37500000 150000000>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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qcom,ufs-bus-bw,name = "ufshc_mem";
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qcom,ufs-bus-bw,num-cases = <12>;
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qcom,ufs-bus-bw,num-paths = <2>;
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qcom,ufs-bus-bw,vectors-KBps =
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/*
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* During HS G3 UFS runs at nominal voltage corner, vote
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* higher bandwidth to push other buses in the data path
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* to run at nominal to achieve max throughput.
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* 4GBps pushes BIMC to run at nominal.
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* 200MBps pushes CNOC to run at nominal.
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* Vote for half of this bandwidth for HS G3 1-lane.
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* For max bandwidth, vote high enough to push the buses
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* to run in turbo voltage corner.
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*/
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<0 0>, <0 0>, /* No vote */
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<922 0>, <1000 0>, /* PWM G1 */
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<1844 0>, <1000 0>, /* PWM G2 */
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<3688 0>, <1000 0>, /* PWM G3 */
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<7376 0>, <1000 0>, /* PWM G4 */
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<127796 0>, <1000 0>, /* HS G1 RA */
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<255591 0>, <1000 0>, /* HS G2 RA */
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<2097152 0>, <102400 0>, /* HS G3 RA */
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<149422 0>, <1000 0>, /* HS G1 RB */
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<298189 0>, <1000 0>, /* HS G2 RB */
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<2097152 0>, <102400 0>, /* HS G3 RB */
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<7643136 0>, <307200 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
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"MAX";
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reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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non-removable;
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status = "disabled";
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qos0 {
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mask = <0xc0>;
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vote = <67>;
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};
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qos1 {
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mask = <0x3f>;
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vote = <67>;
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};
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};
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qmp_aop: qcom,qmp-aop@c300000 {
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compatible = "qcom,qmp-mbox";
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reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
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