mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 06:09:23 -04:00
Merge "clk: qcom: gcc-shima: Add support for ref clocks"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
b6f208ddff
2 changed files with 154 additions and 124 deletions
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@ -1833,6 +1833,19 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
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},
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};
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static struct clk_branch gcc_gpu_iref_en = {
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.halt_reg = 0x8c014,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8c014,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_iref_en",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
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.halt_reg = 0x7100c,
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.halt_check = BRANCH_HALT_VOTED,
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@ -2797,6 +2810,19 @@ static struct clk_branch gcc_titan_rt_throttle_core_clk = {
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},
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};
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static struct clk_branch gcc_ufs_1_clkref_en = {
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.halt_reg = 0x8c000,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8c000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_1_clkref_en",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_ufs_phy_ahb_clk = {
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.halt_reg = 0x77018,
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.halt_check = BRANCH_HALT_VOTED,
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@ -3258,6 +3284,7 @@ static struct clk_regmap *gcc_shima_clocks[] = {
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[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
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[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
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[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
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[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
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[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
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[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
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[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
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@ -3346,6 +3373,7 @@ static struct clk_regmap *gcc_shima_clocks[] = {
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[GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
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&gcc_titan_nrt_throttle_core_clk.clkr,
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[GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
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[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
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[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
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[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
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[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
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@ -40,130 +40,132 @@
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#define GCC_GPU_CFG_AHB_CLK 30
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#define GCC_GPU_GPLL0_CLK_SRC 31
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
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#define GCC_GPU_MEMNOC_GFX_CLK 33
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#define GCC_GPU_SNOC_DVM_GFX_CLK 34
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#define GCC_PCIE0_PHY_RCHNG_CLK 35
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#define GCC_PCIE1_PHY_RCHNG_CLK 36
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#define GCC_PCIE_0_AUX_CLK 37
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#define GCC_PCIE_0_AUX_CLK_SRC 38
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#define GCC_PCIE_0_CFG_AHB_CLK 39
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#define GCC_PCIE_0_MSTR_AXI_CLK 40
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41
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#define GCC_PCIE_0_PIPE_CLK 42
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#define GCC_PCIE_0_PIPE_CLK_SRC 43
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#define GCC_PCIE_0_SLV_AXI_CLK 44
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
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#define GCC_PCIE_1_AUX_CLK 46
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#define GCC_PCIE_1_AUX_CLK_SRC 47
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#define GCC_PCIE_1_CFG_AHB_CLK 48
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#define GCC_PCIE_1_MSTR_AXI_CLK 49
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 50
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#define GCC_PCIE_1_PIPE_CLK 51
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#define GCC_PCIE_1_PIPE_CLK_SRC 52
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#define GCC_PCIE_1_SLV_AXI_CLK 53
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 54
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#define GCC_PCIE_THROTTLE_CORE_CLK 55
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#define GCC_PDM2_CLK 56
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#define GCC_PDM2_CLK_SRC 57
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#define GCC_PDM_AHB_CLK 58
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#define GCC_PDM_XO4_CLK 59
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 60
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 61
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#define GCC_QMIP_DISP_AHB_CLK 62
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 63
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 64
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 65
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#define GCC_QUPV3_WRAP0_CORE_CLK 66
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#define GCC_QUPV3_WRAP0_S0_CLK 67
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 68
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#define GCC_QUPV3_WRAP0_S1_CLK 69
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 70
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#define GCC_QUPV3_WRAP0_S2_CLK 71
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 72
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#define GCC_QUPV3_WRAP0_S3_CLK 73
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 74
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#define GCC_QUPV3_WRAP0_S4_CLK 75
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 76
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#define GCC_QUPV3_WRAP0_S5_CLK 77
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 78
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#define GCC_QUPV3_WRAP0_S6_CLK 79
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 80
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#define GCC_QUPV3_WRAP0_S7_CLK 81
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 82
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 83
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#define GCC_QUPV3_WRAP1_CORE_CLK 84
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#define GCC_QUPV3_WRAP1_S0_CLK 85
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 86
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#define GCC_QUPV3_WRAP1_S1_CLK 87
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88
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#define GCC_QUPV3_WRAP1_S2_CLK 89
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_S3_CLK 91
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92
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#define GCC_QUPV3_WRAP1_S4_CLK 93
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94
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#define GCC_QUPV3_WRAP1_S5_CLK 95
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96
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#define GCC_QUPV3_WRAP1_S6_CLK 97
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 98
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#define GCC_QUPV3_WRAP1_S7_CLK 99
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 100
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104
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#define GCC_SDCC1_AHB_CLK 105
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#define GCC_SDCC1_APPS_CLK 106
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#define GCC_SDCC1_APPS_CLK_SRC 107
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#define GCC_SDCC1_ICE_CORE_CLK 108
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 109
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#define GCC_SDCC2_AHB_CLK 110
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#define GCC_SDCC2_APPS_CLK 111
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#define GCC_SDCC2_APPS_CLK_SRC 112
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#define GCC_SDCC4_AHB_CLK 113
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#define GCC_SDCC4_APPS_CLK 114
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#define GCC_SDCC4_APPS_CLK_SRC 115
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 116
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#define GCC_THROTTLE_PCIE_AHB_CLK 117
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#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 118
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#define GCC_TITAN_RT_THROTTLE_CORE_CLK 119
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#define GCC_UFS_PHY_AHB_CLK 120
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#define GCC_UFS_PHY_AXI_CLK 121
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#define GCC_UFS_PHY_AXI_CLK_SRC 122
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#define GCC_UFS_PHY_ICE_CORE_CLK 123
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 124
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#define GCC_UFS_PHY_PHY_AUX_CLK 125
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 126
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 127
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 128
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 129
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 130
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 131
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 132
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 133
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 134
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#define GCC_USB30_PRIM_MASTER_CLK 135
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 136
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 137
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 138
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 139
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#define GCC_USB30_PRIM_SLEEP_CLK 140
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#define GCC_USB3_PRIM_PHY_AUX_CLK 141
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 142
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 143
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 144
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 145
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#define GCC_VIDEO_AHB_CLK 146
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#define GCC_VIDEO_AXI0_CLK 147
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#define GCC_VIDEO_AXI1_CLK 148
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#define GCC_VIDEO_CVP_THROTTLE_CORE_CLK 149
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#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 150
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#define GCC_VIDEO_XO_CLK 151
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 152
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 154
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 155
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 156
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#define GCC_GPU_IREF_EN 33
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#define GCC_GPU_MEMNOC_GFX_CLK 34
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#define GCC_GPU_SNOC_DVM_GFX_CLK 35
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#define GCC_PCIE0_PHY_RCHNG_CLK 36
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#define GCC_PCIE1_PHY_RCHNG_CLK 37
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#define GCC_PCIE_0_AUX_CLK 38
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#define GCC_PCIE_0_AUX_CLK_SRC 39
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#define GCC_PCIE_0_CFG_AHB_CLK 40
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#define GCC_PCIE_0_MSTR_AXI_CLK 41
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
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#define GCC_PCIE_0_PIPE_CLK 43
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#define GCC_PCIE_0_PIPE_CLK_SRC 44
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#define GCC_PCIE_0_SLV_AXI_CLK 45
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46
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#define GCC_PCIE_1_AUX_CLK 47
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#define GCC_PCIE_1_AUX_CLK_SRC 48
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#define GCC_PCIE_1_CFG_AHB_CLK 49
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#define GCC_PCIE_1_MSTR_AXI_CLK 50
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51
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#define GCC_PCIE_1_PIPE_CLK 52
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#define GCC_PCIE_1_PIPE_CLK_SRC 53
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#define GCC_PCIE_1_SLV_AXI_CLK 54
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 55
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#define GCC_PCIE_THROTTLE_CORE_CLK 56
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#define GCC_PDM2_CLK 57
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#define GCC_PDM2_CLK_SRC 58
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#define GCC_PDM_AHB_CLK 59
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#define GCC_PDM_XO4_CLK 60
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 61
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 62
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#define GCC_QMIP_DISP_AHB_CLK 63
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 64
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 65
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 66
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#define GCC_QUPV3_WRAP0_CORE_CLK 67
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#define GCC_QUPV3_WRAP0_S0_CLK 68
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
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#define GCC_QUPV3_WRAP0_S1_CLK 70
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
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#define GCC_QUPV3_WRAP0_S2_CLK 72
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
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#define GCC_QUPV3_WRAP0_S3_CLK 74
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
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#define GCC_QUPV3_WRAP0_S4_CLK 76
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
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#define GCC_QUPV3_WRAP0_S5_CLK 78
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
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#define GCC_QUPV3_WRAP0_S6_CLK 80
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
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#define GCC_QUPV3_WRAP0_S7_CLK 82
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
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#define GCC_QUPV3_WRAP1_CORE_CLK 85
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#define GCC_QUPV3_WRAP1_S0_CLK 86
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 87
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#define GCC_QUPV3_WRAP1_S1_CLK 88
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 89
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#define GCC_QUPV3_WRAP1_S2_CLK 90
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 91
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#define GCC_QUPV3_WRAP1_S3_CLK 92
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 93
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#define GCC_QUPV3_WRAP1_S4_CLK 94
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 95
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#define GCC_QUPV3_WRAP1_S5_CLK 96
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 97
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#define GCC_QUPV3_WRAP1_S6_CLK 98
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 99
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#define GCC_QUPV3_WRAP1_S7_CLK 100
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 101
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 102
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 103
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 104
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 105
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#define GCC_SDCC1_AHB_CLK 106
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#define GCC_SDCC1_APPS_CLK 107
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#define GCC_SDCC1_APPS_CLK_SRC 108
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#define GCC_SDCC1_ICE_CORE_CLK 109
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 110
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#define GCC_SDCC2_AHB_CLK 111
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#define GCC_SDCC2_APPS_CLK 112
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#define GCC_SDCC2_APPS_CLK_SRC 113
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#define GCC_SDCC4_AHB_CLK 114
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#define GCC_SDCC4_APPS_CLK 115
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#define GCC_SDCC4_APPS_CLK_SRC 116
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 117
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#define GCC_THROTTLE_PCIE_AHB_CLK 118
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#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 119
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#define GCC_TITAN_RT_THROTTLE_CORE_CLK 120
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#define GCC_UFS_1_CLKREF_EN 121
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#define GCC_UFS_PHY_AHB_CLK 122
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#define GCC_UFS_PHY_AXI_CLK 123
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#define GCC_UFS_PHY_AXI_CLK_SRC 124
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#define GCC_UFS_PHY_ICE_CORE_CLK 125
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 126
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#define GCC_UFS_PHY_PHY_AUX_CLK 127
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 128
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 129
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 130
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 131
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 132
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 134
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 135
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 136
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#define GCC_USB30_PRIM_MASTER_CLK 137
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 138
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141
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#define GCC_USB30_PRIM_SLEEP_CLK 142
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#define GCC_USB3_PRIM_PHY_AUX_CLK 143
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 146
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147
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#define GCC_VIDEO_AHB_CLK 148
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#define GCC_VIDEO_AXI0_CLK 149
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#define GCC_VIDEO_AXI1_CLK 150
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#define GCC_VIDEO_CVP_THROTTLE_CORE_CLK 151
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#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 152
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#define GCC_VIDEO_XO_CLK 153
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 154
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 155
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 157
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 158
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/* GCC resets */
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#define GCC_PCIE_0_BCR 0
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