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ARM: dts: msm: Add GPU power levels for Lahaina r2
Add the GPU power levels for Lahaina r2 configuration. Change-Id: I1d7b75cee6ebbbe2d8fb364e3f2485855b6885e4
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1 changed files with 94 additions and 0 deletions
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@ -1,3 +1,97 @@
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&msm_gpu {
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qcom,chipid = <0x06060001>;
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qcom,initial-pwrlevel = <5>;
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <738000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <11>;
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qcom,bus-min-ddr8 = <11>;
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qcom,bus-max-ddr8 = <11>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <676000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <11>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <608000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <11>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <11>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <540000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <6>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <315000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <3>;
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qcom,bus-min-ddr7 = <3>;
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qcom,bus-max-ddr7 = <9>;
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qcom,bus-freq-ddr8 = <3>;
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qcom,bus-min-ddr8 = <3>;
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qcom,bus-max-ddr8 = <8>;
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};
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};
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};
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