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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "irqchip: qcom-pdc: Add IPC logging support"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
bbb789f449
2 changed files with 132 additions and 0 deletions
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@ -11,6 +11,7 @@
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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@ -19,7 +20,11 @@
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/ipc_logging.h>
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#define PDC_MAX_IRQS 168
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#define PDC_IPC_LOG_SZ 2
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#define PDC_MAX_GPIO_IRQS 256
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#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
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@ -36,10 +41,19 @@ struct pdc_pin_region {
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u32 cnt;
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};
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struct spi_cfg_regs {
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u64 start;
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void __iomem *base;
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resource_size_t size;
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bool scm_io;
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};
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static DEFINE_RAW_SPINLOCK(pdc_lock);
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static void __iomem *pdc_base;
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static struct pdc_pin_region *pdc_region;
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static int pdc_region_cnt;
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static struct spi_cfg_regs *spi_cfg;
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static void *pdc_ipc_log;
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static void pdc_reg_write(int reg, u32 i, u32 val)
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{
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@ -84,6 +98,7 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
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enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
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enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
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pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
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ipc_log_string(pdc_ipc_log, "PIN=%d enable=%d", d->hwirq, on);
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raw_spin_unlock(&pdc_lock);
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}
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@ -110,6 +125,7 @@ static void qcom_pdc_gic_mask(struct irq_data *d)
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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ipc_log_string(pdc_ipc_log, "PIN=%d mask", d->hwirq);
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irq_chip_mask_parent(d);
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}
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@ -118,9 +134,64 @@ static void qcom_pdc_gic_unmask(struct irq_data *d)
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if (d->hwirq == GPIO_NO_WAKE_IRQ)
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return;
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ipc_log_string(pdc_ipc_log, "PIN=%d unmask", d->hwirq);
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irq_chip_unmask_parent(d);
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}
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static u32 __spi_pin_read(unsigned int pin)
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{
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void __iomem *cfg_reg = spi_cfg->base + pin * 4;
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u64 scm_cfg_reg = spi_cfg->start + pin * 4;
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if (spi_cfg->scm_io) {
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unsigned int val;
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qcom_scm_io_readl(scm_cfg_reg, &val);
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return val;
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} else {
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return readl_relaxed(cfg_reg);
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}
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}
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static void __spi_pin_write(unsigned int pin, unsigned int val)
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{
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void __iomem *cfg_reg = spi_cfg->base + pin * 4;
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u64 scm_cfg_reg = spi_cfg->start + pin * 4;
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if (spi_cfg->scm_io)
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qcom_scm_io_writel(scm_cfg_reg, val);
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else
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writel_relaxed(val, cfg_reg);
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}
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static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
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{
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int spi = hwirq - 32;
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u32 pin = spi / 32;
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u32 mask = BIT(spi % 32);
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u32 val;
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unsigned long flags;
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if (!spi_cfg)
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return 0;
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if (pin * 4 > spi_cfg->size)
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return -EFAULT;
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raw_spin_lock_irqsave(&pdc_lock, flags);
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val = __spi_pin_read(pin);
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val &= ~mask;
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if (type & IRQ_TYPE_LEVEL_MASK)
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val |= mask;
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__spi_pin_write(pin, val);
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ipc_log_string(pdc_ipc_log,
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"SPI config: GIC-SPI=%d (reg=%d,bit=%d) val=%d",
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spi, pin, spi % 32, type & IRQ_TYPE_LEVEL_MASK);
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raw_spin_unlock_irqrestore(&pdc_lock, flags);
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return 0;
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}
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/*
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* GIC does not handle falling edge or active low. To allow falling edge and
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* active low interrupts to be handled at GIC, PDC has an inverter that inverts
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@ -158,7 +229,9 @@ enum pdc_irq_config_bits {
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static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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{
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int pin_out = d->hwirq;
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int parent_hwirq = d->parent_data->hwirq;
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enum pdc_irq_config_bits pdc_type;
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int ret;
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if (pin_out == GPIO_NO_WAKE_IRQ)
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return 0;
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@ -188,6 +261,15 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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}
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pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
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ipc_log_string(pdc_ipc_log, "Set type: PIN=%d pdc_type=%d gic_type=%d",
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pin_out, pdc_type, type);
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/* Additionally, configure (only) the GPIO in the f/w */
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if (irq_domain_qcom_handle_wakeup(d->domain)) {
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ret = spi_configure_type(parent_hwirq, type);
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if (ret)
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return ret;
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}
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return irq_chip_set_type_parent(d, type);
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}
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@ -274,6 +356,8 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
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parent_fwspec.param[1] = parent_hwirq;
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parent_fwspec.param[2] = type;
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ipc_log_string(pdc_ipc_log, "Alloc: PIN=%d GIC-SPI=%d",
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hwirq, parent_hwirq);
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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@ -321,6 +405,8 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
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parent_fwspec.param[1] = parent_hwirq;
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parent_fwspec.param[2] = type;
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ipc_log_string(pdc_ipc_log, "GPIO alloc: PIN=%d GIC-SPI=%d",
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hwirq, parent_hwirq);
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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@ -374,9 +460,18 @@ static int pdc_setup_pin_mapping(struct device_node *np)
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return 0;
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}
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static int __init qcom_pdc_early_init(void)
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{
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pdc_ipc_log = ipc_log_context_create(PDC_IPC_LOG_SZ, "pdc", 0);
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return 0;
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}
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module_init(qcom_pdc_early_init);
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static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
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struct resource res;
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int ret;
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pdc_base = of_iomap(node, 0);
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@ -407,6 +502,27 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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goto fail;
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}
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ret = of_address_to_resource(node, 1, &res);
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if (!ret) {
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spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL);
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if (!spi_cfg) {
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ret = -ENOMEM;
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goto remove;
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}
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spi_cfg->scm_io = of_find_property(node,
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"qcom,scm-spi-cfg", NULL);
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spi_cfg->size = resource_size(&res);
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if (spi_cfg->scm_io) {
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spi_cfg->start = res.start;
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} else {
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spi_cfg->base = ioremap(res.start, spi_cfg->size);
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if (!spi_cfg->base) {
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ret = -ENOMEM;
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goto remove;
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}
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}
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}
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pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
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IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
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PDC_MAX_GPIO_IRQS,
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@ -424,6 +540,7 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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remove:
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irq_domain_remove(pdc_domain);
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kfree(spi_cfg);
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fail:
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kfree(pdc_region);
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iounmap(pdc_base);
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@ -3,6 +3,8 @@
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#ifndef __QCOM_IRQ_H
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#define __QCOM_IRQ_H
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struct irq_domain;
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#define GPIO_NO_WAKE_IRQ ~0U
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/**
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@ -16,4 +18,17 @@
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#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
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#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)
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/**
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* irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
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* configuration
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* @d: irq domain
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*
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* This QCOM specific irq domain call returns if the interrupt controller
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* requires the interrupt be masked at the child interrupt controller.
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*/
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static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *d)
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{
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return (d->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
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}
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#endif
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