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Merge 3aabccef84 on remote branch

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Change-Id: Ifcdbf2e682e3063b77403ef30263a4177d49eea9
This commit is contained in:
Linux Build Service Account 2020-10-09 01:54:51 -07:00
commit bd3ed34018
70 changed files with 3346 additions and 389 deletions
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4
bindings/arm/msm/msm.txt
View file

@ -56,6 +56,9 @@ SoCs:
- SHIMA
compatible = "qcom,shima"
- YUPIK
compatible = "qcom,yupik"
- LITO
compatible = "qcom,lito"
@ -206,6 +209,7 @@ compatible = "qcom,shima-rumi"
compatible = "qcom,shima-idp"
compatible = "qcom,shima-atp"
compatible = "qcom,shima-qrd"
compatible = "qcom,yupik-rumi"
compatible = "qcom,lito-rumi"
compatible = "qcom,lito-mtp"
compatible = "qcom,lito-cdp"

2
bindings/cnss/cnss-wlan.txt
View file

@ -85,6 +85,8 @@ Optional properties:
- qcom,bus-bw-cfg: Bus bandwidth voting data
- qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490
- cnss-enable-self-recovery: Boolean property to enable self recovery when
recovery is trigeered with reason link down.
Example:

2
bindings/extcon/qcom,pm8941-misc.txt
View file

@ -8,7 +8,7 @@ PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,pm8941-misc";
Definition: Should contain "qcom,pm8941-misc" or "qcom,pmd-vbus-det";
- reg:
Usage: required

6
bindings/hwmon/qcom,amoled-ecm.yaml
View file

@ -53,6 +53,12 @@ properties:
- const: ecm-sdam1
$ref: /schemas/types.yaml#/definitions/string-array
display-panels:
minItems: 1
description: Array of one or more phandles of the display panel(s)
that sends the DRM blank/unblank notifications.
$ref: /schemas/types.yaml#/definitions/phandle-array
required:
- compatible
- reg

2
bindings/iio/adc/qcom,spmi-vadc.txt
View file

@ -15,7 +15,7 @@ VADC node:
Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
Should contain "qcom,pms405-adc" for PMS405 PMIC
Should contain "qcom,spmi-adc5-lite" for PMIC5 ADC-lite driver.
- reg:
Usage: required
Value type: <prop-encoded-array>

62
bindings/input/touchscreen/synaptics_dsx_i2c.txt Normal file
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@ -0,0 +1,62 @@
Synaptics DSXV27 touch controller
Please add this description here: The Synaptics Touch controller is connected to the
host processor via I2C. The controller generates interrupts when the user touches
the panel. The host controller is expected to read the touch coordinates over I2C and
pass the coordinates to the rest of the system.
Required properties:
- compatible : should be "synaptics,dsx-i2c".
- reg : i2c slave address of the device.
- interrupt-parent : parent of interrupt.
- synaptics,irq-gpio : irq gpio.
- synaptics,reset-gpio : reset gpio.
- vdd_supply : digital voltage power supply needed to power device.
- avdd_supply : analog voltage power supply needed to power device.
- synaptics,pwr-reg-name : power reg name of digital voltage.
- synaptics,bus-reg-name : bus reg name of analog voltage.
Optional property:
- synaptics,ub-i2c-addr : addr of ub-i2c.
- synaptics,irq-on-state : status of irq gpio.
- synaptics,cap-button-codes : virtual key code mappings to be used.
- synaptics,vir-button-codes : virtual key code and the response region on panel.
- synaptics,x-flip : modify orientation of the x axis.
- synaptics,y-flip : modify orientation of the y axis.
- synaptics,reset-delay-ms : reset delay for controller (ms), default 100.
- synaptics,power-delay-ms : power delay for controller (ms), default 100.
- synaptics,reset-active-ms : reset active time for controller (ms), default 20.
- synaptics,max-y-for-2d : maximal y value of the panel.
- clock-names : Clock names used for secure touch. They are: "iface_clk", "core_clk"
- clocks : Defined if 'clock-names' DT property is defined. These clocks
are associated with the underlying I2C bus.
Example:
i2c@78b7000 {
status = "ok";
synaptics@4b {
compatible = "synaptics,dsx-i2c";
reg = <0x4b>;
interrupt-parent = <&tlmm>;
interrupts = <65 0x2008>;
vdd_supply = <&pmtitanium_l17>;
avdd_supply = <&pmtitanium_l6>;
synaptics,pwr-reg-name = "vdd";
synaptics,bus-reg-name = "avdd";
synaptics,ub-i2c-addr = <0x2c>;
synaptics,irq-gpio = <&tlmm 65 0x2008>;
synaptics,reset-gpio = <&tlmm 99 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,reset-active-ms = <20>;
synaptics,max-y-for-2d = <1919>; /* remove if no virtual buttons */
synaptics,cap-button-codes = <139 172 158>;
synaptics,vir-button-codes = <139 180 2000 320 160 172 540 2000 320 160 158 900 2000 320 160>;
/* Underlying clocks used by secure touch */
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
};
};

1
bindings/interconnect/qcom,epss-l3.txt
View file

@ -10,6 +10,7 @@ Required properties :
"qcom,lahaina-epss-l3-cpu",
"qcom,shima-epss-l3-cpu",
"qcom,shima-epss-l3-shared";
"qcom,yupik-epss-l3-cpu",
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
- clocks: list of phandle and clock specifier pairs corresponding to

31
bindings/interconnect/qcom,yupik.txt Normal file
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@ -0,0 +1,31 @@
Qualcomm Technologies, Inc. Yupik Network-On-Chip interconnect driver binding
-----------------------------------------------------------
Yupik interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
Required properties :
- compatible : shall contain only one of the following:
"qcom,yupik-aggre1_noc",
"qcom,yupik-aggre2_noc",
"qcom,yupik-clk_virt",
"qcom,yupik-config_noc",
"qcom,yupik-dc_noc",
"qcom,yupik-gem_noc",
"qcom,yupik-lpass_ag_noc",
"qcom,yupik-mc_virt",
"qcom,yupik-mmss_noc",
"qcom,yupik-nsp_noc",
"qcom,yupik-system_noc",
- #interconnect-cells : should contain 1
Examples:
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,yupik-aggre1_noc";
interconnect-cells = <1>;
};

8
bindings/iommu/arm,smmu.txt
View file

@ -156,6 +156,12 @@ conditions.
clients who do not detach, it's not possible to keep regulator
vote while smmu is attached. Type is <u32>.
- qcom,iommu-geometry:
Allow clients to set the available IOVA space for fastmap
clients. The new space created will be a superset of the IOVA
range which was created through the qcom,iommu-dma-addr-pool
DT property.
- (%s)-supply : Phandle of the regulator that should be powered on during
SMMU register access. (%s) is a string from the
qcom,regulator-names property.
@ -231,8 +237,6 @@ conditions.
--- "default":
Pagetable coherency defaults to the coherency setting of the
IOMMU device.
--- "non-coherent":
Pagetables are not coherent nor cached in the system cache..
--- "coherent"
Pagetables are io-coherent.
--- "LLC"

77
bindings/mtd/msm_qpic_nand.txt Normal file
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@ -0,0 +1,77 @@
Qualcomm Technologies, Inc. Parallel Interface controller (QPIC) for NAND devices
Required properties:
- compatible : "qcom,msm-nand".
- reg : should specify QPIC NANDc and BAM physical address range.
- reg-names : should specify relevant names to each reg property defined.
- interrupts : should specify QPIC/BAM interrupt numbers.
- interrupt-names : should specify relevant names to each interrupts property
defined.
- qcom,reg-adjustment-offset : Specify the base adjustment offset value for the
version registers
- qcom,qpic-clk-rpmh: Indicates whether QPIC clock is RPMH controlled clock or
not.
MTD flash partition layout for NAND devices -
Each partition is represented as a sub-node of the qcom,mtd-partitions device.
Each node's name represents the name of the corresponding partition.
This is now completely optional as the partition information is avaialble from
bootloader.
Optional properties:
- reg : boot_cfg. This is needed only on the targets where both NAND and eMMC
devices are supported. On eMMC based builds, NAND cannot be enabled by
default due to the absence of some of its required resources.
- reg : The partition offset and size
- label : The label / name for this partition.
- read-only: This parameter, if present, indicates that this partition
should only be mounted read-only.
- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
below optional properties:
- qcom,msm-bus,name
- qcom,msm-bus,num-cases
- qcom,msm-bus,active-only
- qcom,msm-bus,num-paths
- qcom,msm-bus,vectors-KBps
Examples:
qcom,nand@f9af0000 {
compatible = "qcom,msm-nand";
reg = <0xf9af0000 0x1000>,
<0xf9ac4000 0x8000>,
<0x5e02c 0x4>;
reg-names = "nand_phys",
"bam_phys",
"boot_cfg";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <0 279 0>;
interrupt-names = "bam_irq";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <1>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <91 512 0 0>,
qcom,qpic-clk-rpmh;
};
qcom,mtd-partitions {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x1000>;
read-only;
};
partition@20000 {
label = "userdata";
reg = <0x20000 0x1000>;
};
partition@40000 {
label = "system";
reg = <0x40000 0x1000>;
};
};

9
bindings/pci/pci-msm.txt
View file

@ -229,10 +229,12 @@ interconnects:
link into l1ss sleep while idle in l1ss. If this is omitted,
the default timeout is 100ms.
- qcom,use-19p2mhz-aux-clk:
- qcom,aux-clk-freq:
Usage: optional
Value type: <bool>
Definition: Set PCIe AUX clock frequency to 19.2MHz
Value type: <u32>
Definition: Override reset value for PCIe internal aux clock frequency.
Value will be the actual frequency rounded up to the nearest
decimal. For example, use 17 for 16.6MHz.
- qcom,common-clk-en:
Usage: optional
@ -504,7 +506,6 @@ Example
qcom,link-check-max-count = <40> /* 200ms */
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,use-19p2mhz-aux-clk;
qcom,common-clk-en;
qcom,clk-power-manage-en;
qcom,n-fts = <0x50>;

191
bindings/pinctrl/qcom,yupik-pinctrl.txt Normal file
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@ -0,0 +1,191 @@
Qualcomm Technologies, Inc. YUPIK TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
YUPIK platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,yupik-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- wakeup-parent:
Usage: optional
Value type: <phandle>
Definition: A phandle to the wakeup interrupt controller for the SoC.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio174
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@f000000 {
compatible = "qcom,yupik-pinctrl";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

50
bindings/thermal/qti-cpu-hotplug-cdev.txt Normal file
View file

@ -0,0 +1,50 @@
QTI CPU hotplug cooling devices.
The CPU hotplug cooling device will be used for hotpluging a CPU on a thermal
condition. This cooling device driver can register one cooling device per CPU,
which can be used by thermal zone to mitigate.
Each child node will represent a cooling device and the child node should
point to the CPU, which will be mitigated by that cooling device instance.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: should be "qcom,cpu-hotplug"
Cooling device node:
- qcom,cpu:
Usage: required
Value type: <phandle>
Definition: phandle to the CPU device that this cooling device will
mitigate.
-#cooling-cells:
Usage: required
Value type: <integer>
Definition: Must be 2. Needed for of_thermal as cooling device
identifier. Please refer to
<devicetree/bindings/thermal/thermal.txt> for more
details.
Example:
qcom,cpu-hotplug {
compatible = "qcom,cpu-hotplug";
cpu0_hotplug: cpu0-hotplug {
qcom,cpu = <&CPU0>;
#cooling-cells = <2>;
};
cpu1_hotplug: cpu1-hotplug {
qcom,cpu = <&CPU1>;
#cooling-cells = <2>;
};
cpu2_hotplug: cpu2-hotplug {
qcom,cpu = <&CPU2>;
#cooling-cells = <2>;
};
cpu3_hotplug: cpu3-hotplug {
qcom,cpu = <&CPU3>;
#cooling-cells = <2>;
};
};

9
qcom/Makefile
View file

@ -122,6 +122,15 @@ dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \
shima-idps-digital-mics.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_YUPIK) += \
yupik-rumi-overlay.dtbo
yupik-rumi-overlay.dtbo-base := yupik.dtb
else
dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SM8150) += \
sm8150-cdp-overlay.dtbo \

4
qcom/holi-atp.dtsi
View file

@ -296,4 +296,8 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};

1
qcom/holi-audio-overlay.dtsi
View file

@ -57,6 +57,7 @@
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
qcom,is-always-on = <1>;
wcd937x_tx_slave: wcd937x-tx-slave {
compatible = "qcom,wcd937x-slave";
reg = <0x0A 0x01170223>;

4
qcom/holi-cdp.dtsi
View file

@ -286,4 +286,8 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};

4
qcom/holi-coresight.dtsi
View file

@ -1906,13 +1906,13 @@
};
};
funnel_merge: funnel@8045000 {
funnel_merg: funnel@8045000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb908>;
reg = <0x08045000 0x1000>;
reg-names = "funnel-base";
coresight-name = "coresight-funnel-merge";
coresight-name = "coresight-funnel-merg";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";

37
qcom/holi-mtp-usbc-overlay.dts
View file

@ -9,3 +9,40 @@
qcom,msm-id = <454 0x10000>, <472 0x10000>;
qcom,board-id = <8 1>;
};
&swr0 {
qcom,is_wcd937x = <0>;
};
&wcd937x_tx_slave {
status = "disabled";
};
&wcd937x_rx_slave {
status = "disabled";
};
&wcd937x_codec {
status = "disabled";
};
&wcd938x_tx_slave {
status = "ok"
};
&wcd938x_rx_slave {
status = "ok"
};
&wcd938x_codec {
status = "ok"
};
&holi_snd {
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&wsa881x_i2c_e>,
<&wsa881x_i2c_f>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "wsa-codec0",
"wsa-codec1";
};

108
qcom/holi-mtp-usbc.dtsi
View file

@ -2,6 +2,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "holi-pmic-overlay.dtsi"
#include "display/holi-sde-display-mtp.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
@ -69,10 +71,46 @@
status = "ok"
};
&qupv3_se0_i2c {
status = "ok"
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&holi_snd {
qcom,model = "holi-mtp-usbc-snd-card";
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
fsa4480-i2c-handle = <&fsa4480>;
};
&qupv3_se10_i2c {
status = "ok"
fsa4480: fsa4480@42 {
compatible = "qcom,fsa4480-i2c";
reg = <0x42>;
io-channels = <&pm7250b_charger PSY_IIO_TYPEC_ACCESSORY_MODE>;
io-channel-names = "typec_mode";
qcom,use-power-supply = <1>;
};
};
&soc {
@ -102,6 +140,44 @@
};
};
&pm6150a_amoled {
status = "ok"
};
&qupv3_se8_i2c {
status = "okay";
qcom,i2c-touch-active="synaptics,tcm-i2c";
synaptics_tcm@20 {
compatible = "synaptics,tcm-i2c";
reg = <0x20>;
interrupt-parent = <&tlmm>;
interrupts = <22 0x2008>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
"pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&pmx_ts_release>;
vdd-supply = <&L11A>;
avdd-supply = <&L6A>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,irq-gpio = <&tlmm 22 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,reset-gpio = <&tlmm 21 0x00>;
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
synaptics,reset-delay-ms = <200>;
synaptics,power-delay-ms = <200>;
synaptics,ubl-i2c-addr = <0x20>;
synaptics,extend_report;
synaptics,firmware-name = "synaptics_firmware.img";
panel = <&dsi_rm69299_visionox_amoled_video
&dsi_rm69299_visionox_amoled_cmd>;
};
};
&pm7250b_charger {
status = "ok"
#io-channel-cells = <1>;
@ -135,8 +211,7 @@
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -167,8 +242,7 @@
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
"cp_die_temp";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -214,9 +288,7 @@
qcom,use-cp-iin-sns;
};
&pm6150a_amoled {
status = "ok"
};
#include "camera/holi-camera-sensor-mtp.dtsi"
&pm7250b_charger {
dpdm-supply = <&qusb_phy0>;
@ -266,20 +338,14 @@
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
io-channel-names = "die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
@ -291,14 +357,6 @@
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
@ -337,4 +395,8 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};

28
qcom/holi-mtp.dtsi
View file

@ -192,8 +192,7 @@
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -224,8 +223,7 @@
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
"cp_die_temp";
qcom,battery-data = <&mtp_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -307,20 +305,14 @@
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
io-channel-names = "die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
@ -332,14 +324,6 @@
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};
#include "camera/holi-camera-sensor-mtp.dtsi"
&pm7250b_charger {
@ -392,4 +376,8 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};

72
qcom/holi-qrd.dtsi
View file

@ -269,8 +269,7 @@
<&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>,
<&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_master PSY_IIO_CP_ILIM>,
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>,
<&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>;
<&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
@ -301,8 +300,7 @@
"cp_switcher_en",
"cp_enable",
"cp_ilim",
"cp_die_temp",
"current_capability";
"cp_die_temp";
qcom,battery-data = <&qrd_batterydata>;
qcom,sec-charger-config = <1>;
qcom,auto-recharge-soc = <98>;
@ -400,6 +398,54 @@
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
#io-channel-cells = <1>;
io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>;
io-channel-names = "chg_type";
};
&qusb_phy0 {
qcom,qusb-phy-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x15 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x47 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
qcom,qusb-phy-host-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x15 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x47 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
};
&pm7250b_vadc {
@ -438,20 +484,14 @@
};
&smb1396_div2_cp_master {
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>,
<&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>,
<&pm7250b_vadc ADC5_AMUX_THM2>,
io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>,
<&pm7250b_charger PSY_IIO_SMB_EN_MODE>,
<&pm7250b_charger PSY_IIO_SMB_EN_REASON>;
io-channel-names = "current_capability",
"cp_enable",
"cp_input_current_max",
"die_temp",
io-channel-names = "die_temp",
"real_type",
"adapter_cc_mode",
"pd_current_max",
@ -462,11 +502,3 @@
qcom,parallel-output-mode = <2>; /* VBAT */
status = "ok"
};
&smb1396_slave {
status = "ok"
};
&smb1396_div2_cp_slave {
status = "ok"
};

289
qcom/holi.dtsi
View file

@ -24,6 +24,14 @@
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
@ -340,6 +348,13 @@
label = "dfps_data_region";
};
qcom: ramoops {
compatible = "ramoops";
reg = <0x0 0xd0000000 0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
@ -419,8 +434,21 @@
};
};
sram: sram@fd04480 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mmio-sram";
reg = <0x0 0x0fd04480 0x0 0x80>;
ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scp-shmem";
reg = <0x0 0x0 0x0 0x80>;
};
};
chosen {
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1";
};
};
@ -799,7 +827,7 @@
};
pmic {
qcom,dump-size = <0x10000>;
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
@ -1300,66 +1328,6 @@
qcom,count-unit = <0x10000>;
};
cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>;
};
cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>;
};
cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>;
};
cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>;
};
cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>;
};
cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>;
};
cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc";
governor = "compute";
@ -1368,26 +1336,6 @@
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>;
};
cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0xFD90100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS
&cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>;
};
cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
@ -1412,78 +1360,10 @@
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
qcom,core-dev-table =
< 710400 300000000 >,
< 940800 518400000 >,
< 1190400 748800000 >,
< 1478400 921600000 >,
< 1574400 1305600000 >,
< 1804800 1459000000 >;
};
cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl {
qcom,core-dev-table =
< 1017600 518400000 >,
< 1248000 748800000 >,
< 1536000 921600000 >,
< 1651200 1171200000 >,
< 1804800 1305600000 >,
< 2035200 1459000000 >;
};
cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0>;
qcom,target-dev = <&cpu0_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU1>;
qcom,target-dev = <&cpu1_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU2>;
qcom,target-dev = <&cpu2_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU3>;
qcom,target-dev = <&cpu3_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4>;
qcom,target-dev = <&cpu4_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU5>;
qcom,target-dev = <&cpu5_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
@ -1512,26 +1392,6 @@
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU6 &CPU7>;
cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6>;
qcom,target-dev = <&cpu6_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu6_cpu_l3_tbl>;
};
cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu6_cpu_l3_tbl>;
};
cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6 &CPU7>;
@ -1558,6 +1418,91 @@
};
};
rimps: qcom,rimps@0f400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps";
reg = <0x0f400000 0x10>,
<0x0fd90000 0x2000>;
#mbox-cells = <1>;
interrupts = <0 22 4>;
};
cpu0_grp: qcom,cpu0_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0fd04980 0x300>;
reg-names = "pmu-base";
cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon {
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,cachemiss-ev = <0x17>;
reg = <0xfd90100 0xa0>, <0xfd90320 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 710400 300000000 >,
< 940800 518400000 >,
< 1190400 748800000 >,
< 1478400 921600000 >,
< 1574400 1305600000 >,
< 1804800 1459000000 >;
};
};
cpu6_grp: qcom,cpu6_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU6 &CPU7>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0fd04980 0x300>;
reg-names = "pmu-base";
cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon {
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU6 &CPU7>;
qcom,cachemiss-ev = <0x17>;
qcom,wb-ev = <0x18>;
qcom,access-ev = <0x2B>;
reg = <0xfd90100 0xa0>, <0xfd90320 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 1017600 518400000 >,
< 1248000 748800000 >,
< 1536000 921600000 >,
< 1651200 1171200000 >,
< 1804800 1305600000 >,
< 2035200 1459000000 >;
};
};
scmi: qcom,scmi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,scmi";
mboxes = <&rimps 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
scmi_memlat: protocol@80 {
reg = <0x80>;
#clock-cells = <1>;
};
};
rimps_log: qcom,rimps_log@fd04780 {
compatible = "qcom,rimps-log";
reg = <0x0fd04580 0x200>,
<0x0fd04780 0x200>;
mboxes = <&rimps 1>;
};
tcsr_mutex_block: syscon@340000 {
compatible = "syscon";
reg = <0x340000 0x20000>;
@ -2150,7 +2095,7 @@
"MAX";
iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma = "fastmap";
reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>;
@ -2176,7 +2121,7 @@
reg-names = "hc_mem", "cqhci_mem";
iommus = <&apps_smmu 0x20 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma = "fastmap";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;

36
qcom/lahaina-cdp.dtsi
View file

@ -124,6 +124,32 @@
atmel,display-coords = <0 0 339 729>;
panel = <&dsi_sharp_qhd_plus_dsc_cmd>;
};
synaptics_dsx@22 {
compatible = "synaptics,dsx-i2c";
reg = <0x22>;
interrupt-parent = <&tlmm>;
interrupts = <23 0x2008>;
vdd-supply = <&L8C>;
avdd-supply = <&L3C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,ub-i2c-addr = <0x22>;
synaptics,max-y-for-2d = <1859>;
synaptics,irq-gpio = <&tlmm 23 0x2008>;
synaptics,reset-gpio = <&tlmm 22 0x00>;
synaptics,irq-on-state = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
panel = <&dsi_sharp_qsync_wqhd_cmd &dsi_sharp_qsync_wqhd_video>;
};
};
&sdhc_2 {
@ -182,6 +208,15 @@
status = "ok"
};
&pm8350b_amoled_ecm {
display-panels = <&dsi_sw43404_amoled_cmd
&dsi_sw43404_amoled_video
&dsi_sw43404_amoled_fhd_plus_cmd
&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video
&dsi_sharp_qhd_plus_dsc_cmd>;
};
&pm8350c_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
@ -209,6 +244,7 @@
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
#gpio-cells = <0>;
};
};

2
qcom/lahaina-coresight.dtsi
View file

@ -1007,7 +1007,7 @@
<15 64>,
<20 64>,
<22 32>,
<23 32>,
<23 64>,
<24 32>,
<27 32>,
<28 32>,

3
qcom/lahaina-cvp.dtsi
View file

@ -70,6 +70,7 @@
buffer-types = <0xfff>;
dma-coherent-hint-cached;
qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
qcom,iommu-faults = "non-fatal";
};
@ -81,6 +82,7 @@
buffer-types = <0x741>;
qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
qcom,iommu-vmid = <0xB>;
qcom,iommu-faults = "non-fatal";
};
cvp_secure_pixel_cb {
@ -91,6 +93,7 @@
buffer-types = <0x106>;
qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
qcom,iommu-vmid = <0xA>;
qcom,iommu-faults = "non-fatal";
};
/* Memory Heaps */

16
qcom/lahaina-gpu.dtsi
View file

@ -255,6 +255,9 @@
regulator-names = "vddcx", "vdd";
iommus = <&kgsl_smmu 0x5 0x400>;
qcom,iommu-dma = "disabled";
vddcx-supply = <&gpu_cc_cx_gdsc>;
vdd-supply = <&gpu_cc_gx_gdsc>;
@ -270,18 +273,5 @@
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
gmu_user: gmu_user {
compatible = "qcom,smmu-gmu-user-cb";
iommus = <&kgsl_smmu 0x4 0x400>;
qcom,iommu-dma = "disabled";
};
gmu_kernel: gmu_kernel {
compatible = "qcom,smmu-gmu-kernel-cb";
iommus = <&kgsl_smmu 0x5 0x400>;
qcom,iommu-dma = "disabled";
};
};
};

117
qcom/lahaina-hdk.dtsi
View file

@ -1,5 +1,13 @@
#include "lahaina-qrd-common.dtsi"
&wsa883x_0222 {
status = "disabled";
};
&wsa_spkr_en2 {
status = "disabled";
};
&lahaina_snd {
qcom,model = "lahaina-hdk-snd-card";
@ -60,6 +68,8 @@
qcom,msm-mbhc-usbc-audio-supported = <0>;
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,wsa-max-devs = <1>;
};
&usb1 {
@ -67,3 +77,110 @@
dr_mode = "host";
};
};
&sdhc_2 {
cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
};
&qupv3_se15_i2c {
status = "ok"
lt9611: lt,lt9611@2b {
compatible = "lt,lt9611uxc";
reg = <0x2b>;
interrupt-parent = <&tlmm>;
interrupts = <50 0>;
interrupt-names = "lt_irq";
lt,irq-gpio = <&tlmm 50 0x0>;
lt,reset-gpio = <&tlmm 48 0x0>;
lt,hdmi-3p3-en = <&tlmm 47 0x0>;
lt,hdmi-1p2-en = <&tlmm 49 0x0>;
lt,non-pluggable;
pinctrl-names = "default";
pinctrl-0 = <&lt9611_pins>;
lt,preferred-mode = "1920x1080";
lt,customize-modes {
lt,customize-mode-id@0 {
lt,mode-h-active = <1920>;
lt,mode-h-front-porch = <88>;
lt,mode-h-pulse-width = <44>;
lt,mode-h-back-porch = <148>;
lt,mode-h-active-high;
lt,mode-v-active = <1080>;
lt,mode-v-front-porch = <4>;
lt,mode-v-pulse-width = <5>;
lt,mode-v-back-porch = <36>;
lt,mode-v-active-high;
lt,mode-refresh-rate = <60>;
lt,mode-clock-in-khz = <148500>;
};
lt,customize-mode-id@1 {
lt,mode-h-active = <3840>;
lt,mode-h-front-porch = <176>;
lt,mode-h-pulse-width = <88>;
lt,mode-h-back-porch = <400>;
lt,mode-h-active-high;
lt,mode-v-active = <2160>;
lt,mode-v-front-porch = <8>;
lt,mode-v-pulse-width = <10>;
lt,mode-v-back-porch = <72>;
lt,mode-v-active-high;
lt,mode-refresh-rate = <60>;
lt,mode-clock-in-khz = <608040>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt9611_in_0: endpoint {
remote-endpoint = <&ext_dsi_0_out>;
};
};
port@1 {
reg = <1>;
lt9611_in_1: endpoint {
remote-endpoint = <&ext_dsi_1_out>;
};
};
};
};
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ext_dsi_0_out: endpoint {
remote-endpoint = <&lt9611_in_0>;
};
};
};
};
&sde_dsi1 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
ext_dsi_1_out: endpoint {
remote-endpoint = <&lt9611_in_1>;
};
};
};
};

9
qcom/lahaina-mtp.dtsi
View file

@ -163,6 +163,14 @@
status = "ok"
};
&pm8350b_amoled_ecm {
display-panels = <&dsi_sw43404_amoled_cmd
&dsi_sw43404_amoled_video
&dsi_sw43404_amoled_fhd_plus_cmd
&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
};
&pm8350c_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
@ -190,6 +198,7 @@
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
#gpio-cells = <0>;
};
};

2
qcom/lahaina-pcie.dtsi
View file

@ -103,7 +103,6 @@
qcom,drv-supported;
qcom,l1ss-sleep-disable = <0x1>;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,use-19p2mhz-aux-clk;
qcom,no-l0s-supported;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
@ -330,7 +329,6 @@
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,use-19p2mhz-aux-clk;
qcom,wr-halt-size = <0x8>;
qcom,no-l0s-supported;
qcom,slv-addr-space-size = <0x20000000>;

13
qcom/lahaina-pinctrl.dtsi
View file

@ -380,6 +380,19 @@
};
};
lt9611_pins: lt9611_pins {
mux {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
function = "gpio";
};
config {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
drive-strength = <8>;
bias-disable = <0>;
};
};
nfc {
nfc_int_active: nfc_int_active {
/* active state */

82
qcom/lahaina-pmic-overlay.dtsi
View file

@ -1,4 +1,5 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-smb139x.h>
#include "pmk8350.dtsi"
#include "pm8350.dtsi"
@ -330,6 +331,60 @@
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350b_chg_temp {
reg = <PM8350B_ADC7_CHG_TEMP>;
label = "pm8350b_chg_temp";
qcom,pre-scaling = <1 1>;
};
pm8350b_iin_fb {
reg = <PM8350B_ADC7_IIN_FB>;
label = "pm8350b_iin_fb";
qcom,pre-scaling = <32 100>;
};
pm8350b_ichg_fb {
reg = <PM8350B_ADC7_ICHG_FB>;
label = "pm8350b_ichg_fb";
qcom,pre-scaling = <1000 305185>;
};
smb139x_1_smb_temp {
reg = <SMB139x_1_ADC7_SMB_TEMP>;
label = "smb139x_1_smb_temp";
qcom,pre-scaling = <1 1>;
};
smb139x_1_ichg_smb {
reg = <SMB139x_1_ADC7_ICHG_SMB>;
label = "smb139x_1_ichg_smb";
qcom,pre-scaling = <14 100>;
};
smb139x_1_iin_smb {
reg = <SMB139x_1_ADC7_IIN_SMB>;
label = "smb139x_1_iin_smb";
qcom,pre-scaling = <28 100>;
};
smb139x_2_smb_temp {
reg = <SMB139x_2_ADC7_SMB_TEMP>;
label = "smb139x_2_smb_temp";
qcom,pre-scaling = <1 1>;
};
smb139x_2_ichg_smb {
reg = <SMB139x_2_ADC7_ICHG_SMB>;
label = "smb139x_2_ichg_smb";
qcom,pre-scaling = <14 100>;
};
smb139x_2_iin_smb {
reg = <SMB139x_2_ADC7_IIN_SMB>;
label = "smb139x_2_iin_smb";
qcom,pre-scaling = <28 100>;
};
};
&pm8350_tz {
@ -439,6 +494,12 @@
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
@ -546,6 +607,27 @@
};
};
};
xo-therm-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
trips {
xo_config0: active-config0 {
temperature = <78000>;
hysteresis = <8000>;
type = "passive";
};
xo_config1: active-config1 {
temperature = <80000>;
hysteresis = <10000>;
type = "passive";
};
};
};
};
&soc {

6
qcom/lahaina-qrd-common.dtsi
View file

@ -105,6 +105,7 @@
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
#gpio-cells = <0>;
};
};
@ -299,6 +300,11 @@
};
};
&pm8350b_amoled_ecm {
display-panels = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
};
&soc {
gpio_keys {
compatible = "gpio-keys";

9
qcom/lahaina-qupv3.dtsi
View file

@ -34,7 +34,8 @@
<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
<MASTER_QUP_0 SLAVE_EBI1>;
iommus = <&apps_smmu 0x5a3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
};
@ -424,7 +425,8 @@
<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
<MASTER_QUP_1 SLAVE_EBI1>;
iommus = <&apps_smmu 0x43 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
};
@ -762,7 +764,8 @@
<MASTER_QUP_CORE_2 SLAVE_QUP_CORE_2>,
<MASTER_QUP_2 SLAVE_EBI1>;
iommus = <&apps_smmu 0x5e3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
};

12
qcom/lahaina-thermal-modem.dtsi
View file

@ -465,13 +465,13 @@
trips {
mdmss10_config: active-config0 {
temperature = <95000>;
hysteresis = <5000>;
hysteresis = <3000>;
type = "passive";
};
mdmss11_config: active-config1 {
temperature = <100000>;
hysteresis = <5000>;
temperature = <98000>;
hysteresis = <2000>;
type = "passive";
};
@ -508,13 +508,13 @@
trips {
mdmss20_config: active-config0 {
temperature = <95000>;
hysteresis = <5000>;
hysteresis = <3000>;
type = "passive";
};
mdmss21_config: active-config1 {
temperature = <100000>;
hysteresis = <5000>;
temperature = <98000>;
hysteresis = <2000>;
type = "passive";
};

56
qcom/lahaina-thermal-overlay.dtsi
View file

@ -296,4 +296,60 @@
};
};
};
xo-therm-step {
cooling-maps {
cpu4_freq_cdev {
trip = <&xo_config0>;
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu7_freq_cdev {
trip = <&xo_config0>;
cooling-device = <&CPU7 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu4_iso_cdev {
trip = <&xo_config0>;
cooling-device = <&cpu4_isolate 1 1>;
};
cpu5_iso_cdev {
trip = <&xo_config0>;
cooling-device = <&cpu5_isolate 1 1>;
};
cpu6_iso_cdev {
trip = <&xo_config0>;
cooling-device = <&cpu6_isolate 1 1>;
};
cpu7_iso_cdev {
trip = <&xo_config0>;
cooling-device = <&cpu7_isolate 1 1>;
};
cpu4_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
cpu5_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
cpu6_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
cpu7_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
};
};
};

304
qcom/lahaina-thermal.dtsi
View file

@ -30,12 +30,29 @@
csr-id = <1 3 5>;
};
cx_sdpm@0x00634000 {
compatible = "qcom,sdpm";
reg = <0x00634000 0x1000>;
clock-names = "cam_cc_csi0phytiimer", "ufs_phy";
clocks = <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_gcc GCC_UFS_PHY_AXI_CLK_SRC>;
cam_cc_csi0phytiimer-supply = <&cam_cc_ipe_0_gdsc>;
csr-id = <5 7>;
};
mx_pe: mx_rdpm_pe@0x00637000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00637000 0x1000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
};
cx_pe: cx_rdpm_pe@0x00635000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00635000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
};
&cpufreq_hw {
@ -82,6 +99,49 @@
};
};
qcom,cpu-hotplug {
compatible = "qcom,cpu-hotplug";
cpu0_hotplug: cpu0-hotplug {
qcom,cpu = <&CPU0>;
#cooling-cells = <2>;
};
cpu1_hotplug: cpu1-hotplug {
qcom,cpu = <&CPU1>;
#cooling-cells = <2>;
};
cpu2_hotplug: cpu2-hotplug {
qcom,cpu = <&CPU2>;
#cooling-cells = <2>;
};
cpu3_hotplug: cpu3-hotplug {
qcom,cpu = <&CPU3>;
#cooling-cells = <2>;
};
cpu4_hotplug: cpu4-hotplug {
qcom,cpu = <&CPU4>;
#cooling-cells = <2>;
};
cpu5_hotplug: cpu5-hotplug {
qcom,cpu = <&CPU5>;
#cooling-cells = <2>;
};
cpu6_hotplug: cpu6-hotplug {
qcom,cpu = <&CPU6>;
#cooling-cells = <2>;
};
cpu7_hotplug: cpu7-hotplug {
qcom,cpu = <&CPU7>;
#cooling-cells = <2>;
};
};
qcom,limits-dcvs {
compatible = "qcom,msm-hw-limits";
isens_vref_0p8-supply = <&pm8350_l5_ao>;
@ -718,6 +778,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu00_config1: cpu00-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -725,6 +791,17 @@
trip = <&cpu00_config>;
cooling-device = <&cpu0_isolate 1 1>;
};
cpu00_cdev1 {
trip = <&cpu00_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu00_cdev2 {
trip = <&cpu00_config1>;
cooling-device = <&cpu0_hotplug 1 1>;
};
};
};
@ -739,6 +816,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu01_config1: cpu01-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -746,6 +829,17 @@
trip = <&cpu01_config>;
cooling-device = <&cpu1_isolate 1 1>;
};
cpu01_cdev1 {
trip = <&cpu01_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu01_cdev2 {
trip = <&cpu01_config1>;
cooling-device = <&cpu1_hotplug 1 1>;
};
};
};
@ -760,6 +854,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu02_config1: cpu02-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -767,6 +867,17 @@
trip = <&cpu02_config>;
cooling-device = <&cpu2_isolate 1 1>;
};
cpu02_cdev1 {
trip = <&cpu02_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu02_cdev2 {
trip = <&cpu02_config1>;
cooling-device = <&cpu2_hotplug 1 1>;
};
};
};
@ -781,6 +892,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu03_config1: cpu03-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -788,6 +905,17 @@
trip = <&cpu03_config>;
cooling-device = <&cpu3_isolate 1 1>;
};
cpu03_cdev1 {
trip = <&cpu03_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu03_cdev2 {
trip = <&cpu03_config1>;
cooling-device = <&cpu3_hotplug 1 1>;
};
};
};
@ -798,6 +926,12 @@
thermal-governor = "step_wise";
trips {
cpu10_config: cpu10-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu10_config1: cpu10-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -815,6 +949,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu10_cdev2 {
trip = <&cpu10_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
};
};
@ -825,6 +964,12 @@
thermal-governor = "step_wise";
trips {
cpu11_config: cpu11-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu11_config1: cpu11-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -842,6 +987,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu11_cdev2 {
trip = <&cpu11_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
};
};
@ -852,6 +1002,12 @@
thermal-governor = "step_wise";
trips {
cpu12_config: cpu12-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu12_config1: cpu12-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -869,6 +1025,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu12_cdev2 {
trip = <&cpu12_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
};
};
@ -879,6 +1040,12 @@
thermal-governor = "step_wise";
trips {
cpu13_config: cpu13-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu13_config1: cpu13-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -896,6 +1063,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu13_cdev2 {
trip = <&cpu13_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
};
};
@ -906,6 +1078,12 @@
thermal-governor = "step_wise";
trips {
cpu14_config: cpu14-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu14_config1: cpu14-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -923,6 +1101,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu14_cdev2 {
trip = <&cpu14_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
};
};
@ -933,6 +1116,12 @@
thermal-governor = "step_wise";
trips {
cpu15_config: cpu15-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu15_config1: cpu15-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -950,6 +1139,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu15_cdev2 {
trip = <&cpu15_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
};
};
@ -960,6 +1154,12 @@
thermal-governor = "step_wise";
trips {
cpu16_config: cpu16-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu16_config1: cpu16-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -971,6 +1171,17 @@
trip = <&cpu16_config>;
cooling-device = <&cpu7_isolate 1 1>;
};
cpu16_cdev1 {
trip = <&cpu16_config>;
cooling-device = <&CPU7 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu16_cdev2 {
trip = <&cpu16_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
};
};
@ -981,6 +1192,12 @@
thermal-governor = "step_wise";
trips {
cpu17_config: cpu17-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu17_config1: cpu17-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -992,6 +1209,17 @@
trip = <&cpu17_config>;
cooling-device = <&cpu7_isolate 1 1>;
};
cpu17_cdev1 {
trip = <&cpu17_config>;
cooling-device = <&CPU7 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu17_cdev2 {
trip = <&cpu17_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
};
};
@ -1158,6 +1386,12 @@
hysteresis = <1>;
type = "passive";
};
mx_pe_config3: mx-pe-config3 {
temperature = <3>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
@ -1170,6 +1404,76 @@
trip = <&mx_pe_config2>;
cooling-device = <&msm_gpu 1 1>;
};
mx_pe_cdev_3 {
trip = <&mx_pe_config3>;
cooling-device = <&modem_tj 1 1>;
};
};
};
cx-pe-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&cx_pe>;
thermal-governor = "step_wise";
trips {
cx_pe_config1: cx-pe-config1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config2: cx-pe-config2 {
temperature = <2>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config3: cx-pe-config3 {
temperature = <3>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config4: cx-pe-config4 {
temperature = <4>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config5: cx-pe-config5 {
temperature = <5>;
hysteresis = <2>;
type = "passive";
};
};
cooling-maps {
cx_pe_cdev_1 {
trip = <&cx_pe_config1>;
cooling-device = <&cdsp_sw 1 1>;
};
cx_pe_cdev_2 {
trip = <&cx_pe_config2>;
cooling-device = <&cdsp_sw 2 2>;
};
cx_pe_cdev_3 {
trip = <&cx_pe_config3>;
cooling-device = <&cdsp_sw 3 3>;
};
cx_pe_cdev_4 {
trip = <&cx_pe_config4>;
cooling-device = <&modem_tj 1 1>;
};
cx_pe_cdev_5 {
trip = <&cx_pe_config5>;
cooling-device = <&cdsp_sw 4 4>;
};
};
};
};

5
qcom/lahaina-v2.dtsi
View file

@ -126,6 +126,11 @@
compatible = "qcom,lahaina-camcc-v2", "syscon";
};
&usb_qmp_phy {
vdd-supply = <&pm8350_l5>;
qcom,vdd-voltage-level = <0 880000 888000>;
};
#include "lahaina-v2-gpu.dtsi"
&cpu0_cpu_l3_tbl {

2
qcom/lahaina-vm-qrd.dtsi
View file

@ -5,6 +5,8 @@
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <566>;

2
qcom/lahaina-vm.dtsi
View file

@ -15,7 +15,7 @@
};
chosen {
bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8";
bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8";
linux,initrd-start = <0x2a900000>;
linux,initrd-end = <0x2b100000>; /* 8 MB */
kaslr-seed = <0xfeedbeef 0xc0def00d>;

25
qcom/lahaina.dtsi
View file

@ -573,7 +573,8 @@
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x350>;
iommus = <&apps_smmu 0x1826 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
@ -2346,7 +2347,6 @@
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
@ -2359,7 +2359,6 @@
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>;
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
@ -2371,7 +2370,6 @@
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
clock-names = "iface";
#clock-cells = <1>;
@ -4245,6 +4243,12 @@
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_slpi>,
@ -4285,6 +4289,12 @@
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,slpi_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
@ -4313,6 +4323,12 @@
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
@ -5345,6 +5361,7 @@
/* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */
qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>;
use-pm-domain;
cnss-enable-self-recovery;
vdd-wlan-aon-supply = <&S2E>;
qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;

1
qcom/msm-arm-smmu-shima.dtsi
View file

@ -9,6 +9,7 @@
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
qcom,split-tables;
#global-interrupts = <2>;
#size-cells = <1>;
#address-cells = <1>;

1
qcom/pm7250b.dtsi
View file

@ -29,6 +29,7 @@
qcom,thermal-mitigation = <5400000 4500000 4000000
3500000 3000000 2500000 2000000 1500000
1000000 500000>;
qcom,hvdcp2-max-icl-ua = <2000000>;
qcom,chgr@1000 {
reg = <0x1000>;

2
qcom/pm8350b.dtsi
View file

@ -208,7 +208,7 @@
};
};
qcom,amoled-ecm@f900 {
pm8350b_amoled_ecm: qcom,amoled-ecm@f900 {
compatible = "qcom,amoled-ecm";
reg = <0xf900>;
nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1";

7
qcom/pmx65.dtsi
View file

@ -34,6 +34,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
vbus_detect: qcom,pmd-vbus-det@1500 {
compatible = "qcom,pmd-vbus-det";
reg = <0x1500>;
interrupts = <0x1 0x15 0x0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_vbus";
};
};
};

3
qcom/sdxlemur-cdp.dtsi
View file

@ -4,3 +4,6 @@
};
&qnand_1 {
status = "ok"
};

3
qcom/sdxlemur-mtp.dtsi
View file

@ -4,3 +4,6 @@
};
&qnand_1 {
status = "ok"
};

144
qcom/sdxlemur-pcie.dtsi
View file

@ -96,10 +96,152 @@
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <0>;
qcom,pcie-phy-ver = <1101>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;
qcom,phy-sequence = <0x1240 0x03 0x0
0x1010 0x01 0x0
0x101c 0x31 0x0
0x1020 0x01 0x0
0x1024 0xde 0x0
0x1028 0x07 0x0
0x1030 0x97 0x0
0x1034 0x0c 0x0
0x1044 0x14 0x0
0x1048 0x90 0x0
0x1058 0x0f 0x0
0x1074 0x06 0x0
0x1078 0x06 0x0
0x107c 0x16 0x0
0x1080 0x16 0x0
0x1084 0x36 0x0
0x1088 0x36 0x0
0x1094 0x08 0x0
0x10a4 0x46 0x0
0x10a8 0x04 0x0
0x10ac 0x0a 0x0
0x10b0 0x1a 0x0
0x10b4 0x14 0x0
0x10b8 0x34 0x0
0x10bc 0x82 0x0
0x10c4 0xd0 0x0
0x10cc 0x55 0x0
0x10d0 0x55 0x0
0x10d4 0x03 0x0
0x10d8 0x55 0x0
0x10dc 0x55 0x0
0x10e0 0x05 0x0
0x110c 0x02 0x0
0x1154 0x34 0x0
0x1158 0x12 0x0
0x115c 0x00 0x0
0x1168 0x0a 0x0
0x116c 0x04 0x0
0x119c 0x88 0x0
0x1174 0x20 0x0
0x117c 0x06 0x0
0x11a0 0x14 0x0
0x11a8 0x0f 0x0
0x0220 0x16 0x0
0x03c0 0x38 0x0
0x0a20 0x16 0x0
0x0bc0 0x38 0x0
0x0364 0xcc 0x0
0x036c 0xcc 0x0
0x0378 0x31 0x0
0x037c 0xc5 0x0
0x0380 0xcc 0x0
0x0384 0xb6 0x0
0x0388 0xc2 0x0
0x038c 0x17 0x0
0x0390 0xfb 0x0
0x0394 0x0f 0x0
0x039c 0xee 0x0
0x03a0 0xbf 0x0
0x03a4 0x80 0x0
0x03a8 0x81 0x0
0x03ac 0xdf 0x0
0x03b0 0x5f 0x0
0x0b64 0xcc 0x0
0x0b6c 0xcc 0x0
0x0b78 0x31 0x0
0x0b7c 0xc5 0x0
0x0b80 0xcc 0x0
0x0b84 0xb6 0x0
0x0b88 0xc2 0x0
0x0b8c 0x17 0x0
0x0b90 0xfb 0x0
0x0b94 0x0f 0x0
0x0b9c 0xee 0x0
0x0ba0 0xbf 0x0
0x0ba4 0x80 0x0
0x0ba8 0x81 0x0
0x0bac 0xdf 0x0
0x0bb0 0x5f 0x0
0x03b4 0x20 0x0
0x022c 0x3f 0x0
0x0230 0x2d 0x0
0x0bb4 0x20 0x0
0x0a2c 0x3f 0x0
0x0a30 0x2d 0x0
0x0078 0x05 0x0
0x007c 0xf6 0x0
0x0878 0x05 0x0
0x087c 0xf6 0x0
0x0290 0x05 0x0
0x0a90 0x05 0x0
0x03f8 0x1f 0x0
0x0400 0x1f 0x0
0x0408 0x1f 0x0
0x0410 0x1f 0x0
0x0418 0x1f 0x0
0x0420 0x1f 0x0
0x03f4 0x1f 0x0
0x03fc 0x1f 0x0
0x0404 0x1f 0x0
0x0bf8 0x1f 0x0
0x0c00 0x1f 0x0
0x0c08 0x1f 0x0
0x0c10 0x1f 0x0
0x0c18 0x1f 0x0
0x0c20 0x1f 0x0
0x0bf4 0x1f 0x0
0x0bfc 0x1f 0x0
0x0c04 0x1f 0x0
0x0208 0x0c 0x0
0x0a08 0x0c 0x0
0x020c 0x0a 0x0
0x0a0c 0x0a 0x0
0x02dc 0x0a 0x0
0x0adc 0x0a 0x0
0x0308 0x0b 0x0
0x0b08 0x0b 0x0
0x027c 0x1f 0x0
0x0a7c 0x1f 0x0
0x02b4 0x00 0x0
0x0ab4 0x00 0x0
0x02ec 0x0d 0x0
0x0aec 0x0d 0x0
0x02c4 0x00 0x0
0x02c8 0x1f 0x0
0x0ac4 0x00 0x0
0x0ac8 0x1f 0x0
0x0030 0x1a 0x0
0x0034 0x0c 0x0
0x0830 0x1a 0x0
0x0834 0x0c 0x0
0x141c 0xc1 0x0
0x1490 0x00 0x0
0x13e0 0x16 0x0
0x13e4 0x22 0x0
0x1508 0x02 0x0
0x14a0 0x16 0x0
0x1584 0x28 0x0
0x1370 0x2e 0x0
0x155c 0x2e 0x0
0x1200 0x00 0x0
0x1244 0x03 0x0>;
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;

210
qcom/sdxlemur-pmic-overlay.dtsi
View file

@ -1,8 +1,210 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pmx65.h>
#include "pmk8350.dtsi"
#include "pmx65.dtsi"
#include "pm7250b.dtsi"
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
&pmk8350_vadc {
/delete-node/ pm8350_ref_gnd;
/delete-node/ pm8350_vref_1p25;
/delete-node/ pm8350_die_temp;
/delete-node/ pm8350_vph_pwr;
/delete-node/ pm8350b_ref_gnd;
/delete-node/ pm8350b_vref_1p25;
/delete-node/ pm8350b_die_temp;
/delete-node/ pm8350b_vph_pwr;
/delete-node/ pm8350b_vbat_sns;
/delete-node/ pmr735a_ref_gnd;
/delete-node/ pmr735a_vref_1p25;
/delete-node/ pmr735a_die_temp;
/delete-node/ pmr735b_ref_gnd;
/delete-node/ pmr735b_vref_1p25;
/delete-node/ pmr735b_die_temp;
pmx65_pa_therm1 {
reg = <PMX65_ADC7_AMUX_THM1_100K_PU>;
label = "pmx65_pa_therm1";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmx65_pa_therm2 {
reg = <PMX65_ADC7_AMUX_THM2_100K_PU>;
label = "pmx65_pa_therm2";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmx65_mdm_case_therm {
reg = <PMX65_ADC7_AMUX_THM3_100K_PU>;
label = "pmx65_mdm_case_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmx65_ambient_therm {
reg = <PMX65_ADC7_AMUX_THM4_100K_PU>;
label = "pmx65_ambient_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmx65_qtm_skin_therm {
reg = <PMX65_ADC7_AMUX_THM6_100K_PU>;
label = "pmx65_qtm_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pmk8350_adc_tm {
io-channels = <&pmk8350_vadc PMX65_ADC7_AMUX_THM1_100K_PU>,
<&pmk8350_vadc PMX65_ADC7_AMUX_THM2_100K_PU>,
<&pmk8350_vadc PMX65_ADC7_AMUX_THM3_100K_PU>,
<&pmk8350_vadc PMX65_ADC7_AMUX_THM4_100K_PU>,
<&pmk8350_vadc PMX65_ADC7_AMUX_THM6_100K_PU>;
pmx65_pa_therm1 {
reg = <PMX65_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmx65_pa_therm2 {
reg = <PMX65_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmx65_mdm_case_therm {
reg = <PMX65_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmx65_ambient_therm {
reg = <PMX65_ADC7_AMUX_THM4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmx65_qtm_skin_therm {
reg = <PMX65_ADC7_AMUX_THM6_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
modem-lte-sub6-pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM1_100K_PU>;
wake-capable-sensor;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-lte-sub6-pa2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM2_100K_PU>;
wake-capable-sensor;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-skin-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM3_100K_PU>;
wake-capable-sensor;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-ambient-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM4_100K_PU>;
wake-capable-sensor;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-beamer-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM6_100K_PU>;
wake-capable-sensor;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

8
qcom/sdxlemur-rumi.dtsi
View file

@ -13,8 +13,8 @@
compatible = "qcom,usb-emu-phy";
reg = <0x0a720000 0x9500>;
qcom,emu-init-seq = <0xfffdf 0x4
0xfffd0 0x4
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x101f0 0x20
@ -26,6 +26,10 @@
};
&qnand_1 {
status = "ok"
};
&usb {
dwc3@a600000 {
usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;

79
qcom/sdxlemur.dtsi
View file

@ -103,6 +103,13 @@
};
soc: soc { };
firmware: firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
};
&soc {
@ -226,6 +233,11 @@
qcom,wakeup-enable;
};
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
@ -340,22 +352,6 @@
};
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
aopcc: clock-controller@0 {
compatible = "qcom,aop-qmp-clk";
mboxes = <&qmp_aop 0>;
@ -363,16 +359,16 @@
#clock-cells = <1>;
};
rpmhcc: clock-controller@1 {
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
gcc: clock-controller@0x100000 {
compatible = "qcom,sdxlemur-gcc", "syscon";
reg = <0x100000 0x1f7400>;
reg-name = "cc_base";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -390,6 +386,23 @@
status = "ok"
};
qnand_1: nand@1b00000 {
compatible = "qcom,msm-nand";
reg = <0x01b00000 0x1000>,
<0x01b04000 0x1c000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_QPIC_CLK>;
status = "disabled";
};
apsscc: clock-controller@17808000 {
compatible = "qcom,dummycc";
clock-output-names = "apsscc_clocks";
@ -419,6 +432,11 @@
system_pm {
compatible = "qcom,system-pm";
};
rpmhcc: clock-controller@1 {
compatible = "qcom,sdxlemur-rpmh-clk";
#clock-cells = <1>;
};
};
pdc: interrupt-controller@b210000 {
@ -432,13 +450,13 @@
/* GCC GDSCs */
gcc_pcie_gdsc: qcom,gdsc@143004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x143004 0x4>;
regulator-name = "gcc_pcie_gdsc";
};
gcc_usb30_gdsc: qcom,gdsc@117004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x117004 0x4>;
regulator-name = "gcc_usb30_gdsc";
};
@ -477,6 +495,11 @@
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
cache-controller@9200000 {
compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
reg = <0x9200000 0x50000>;

10
qcom/shima-audio-overlay.dtsi
View file

@ -33,7 +33,6 @@
qcom,va-dmic-sample-rate = <600000>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,is-used-swr-gpio = <0>;
qcom,disable-afe-wakeup-event-listener = <1>;
};
tx_macro: tx-macro@3220000 {
@ -44,6 +43,7 @@
<&clock_audio_tx_2 0>;
qcom,tx-swr-gpios = <&tx_swr_gpios>;
qcom,tx-dmic-sample-rate = <2400000>;
qcom,disable-afe-wakeup-event-listener = <1>;
swr2: tx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
@ -247,7 +247,7 @@
qcom,wcn-bt = <1>;
qcom,tdm-max-slots = <8>;
qcom,wcd-disabled = <0>;
qcom,ext-disp-audio-rx = <0>;
qcom,ext-disp-audio-rx = <1>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS3",
@ -310,10 +310,12 @@
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
<&wsa883x_0221>, <&wsa883x_0222>,
<&ext_disp_audio_codec>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
"wsa-codec1", "wsa-codec2",
"msm-ext-disp-audio-codec-rx";
qcom,wsa-max-devs = <2>;
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>;

1
qcom/shima-audio.dtsi
View file

@ -109,6 +109,7 @@
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
&rx_swr_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <172>;
#gpio-cells = <0>;
};

14
qcom/shima-gdsc.dtsi
View file

@ -32,6 +32,13 @@
status = "disabled";
};
gcc_usb30_sec_gdsc: qcom,gdsc@19e004 {
compatible = "qcom,gdsc";
reg = <0x19e004 0x4>;
regulator-name = "gcc_usb30_sec_gdsc";
status = "disabled";
};
hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
compatible = "qcom,gdsc";
reg = <0x17d05c 0x4>;
@ -220,4 +227,11 @@
regulator-name = "video_cc_mvs1c_gdsc";
status = "disabled";
};
video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {
compatible = "qcom,gdsc";
reg = <0xaaf2004 0x4>;
regulator-name = "video_cc_mvsc_gdsc";
status = "disabled";
};
};

90
qcom/shima-gpu.dtsi
View file

@ -37,12 +37,12 @@
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"apb_pclk",
"gpu_cc_hlos1_vote_gpu_smmu_clk",
"gpu_cc_hlos1_vote_gpu_smmu",
"gpu_cc_cx_gmu",
"gpu_cc_hub_aon",
"gpu_cc_hub_cx_int";
qcom,chipid = <0x06060001>;
qcom,chipid = <0x06060010>;
qcom,no-nap;
@ -52,6 +52,8 @@
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
@ -141,10 +143,24 @@
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <4>;
qcom,initial-pwrlevel = <5>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <747000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -152,13 +168,13 @@
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -171,8 +187,8 @@
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -185,8 +201,8 @@
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -199,8 +215,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@ -305,10 +321,24 @@
#size-cells = <0>;
qcom,speed-bin = <158>;
qcom,initial-pwrlevel = <4>;
qcom,initial-pwrlevel = <5>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <747000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -316,13 +346,13 @@
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -335,8 +365,8 @@
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -349,8 +379,8 @@
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -363,8 +393,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@ -420,6 +450,9 @@
regulator-names = "vddcx", "vdd";
iommus = <&kgsl_smmu 0x5 0x400>;
qcom,iommu-dma = "disabled";
vddcx-supply = <&gpu_cx_gdsc>;
vdd-supply = <&gpu_gx_gdsc>;
@ -436,18 +469,5 @@
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
gmu_user: gmu_user {
compatible = "qcom,smmu-gmu-user-cb";
iommus = <&kgsl_smmu 0x4 0x400>;
qcom,iommu-dma = "disabled";
};
gmu_kernel: gmu_kernel {
compatible = "qcom,smmu-gmu-kernel-cb";
iommus = <&kgsl_smmu 0x5 0x400>;
qcom,iommu-dma = "disabled";
};
};
};

2
qcom/shima-idp.dtsi
View file

@ -77,7 +77,7 @@
vdd-io-supply = <&L6C>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
qcom,vdd-io-current-level = <0 30000>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};

5
qcom/shima-ion.dtsi
View file

@ -53,5 +53,10 @@
memory-region = <&audio_cma_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@3 { /* NON SECURE DISPLAY HEAP */
reg = <ION_DISPLAY_HEAP_ID>;
memory-region = <&non_secure_display_memory>;
qcom,ion-heap-type = "DMA";
};
};
};

14
qcom/shima-pinctrl.dtsi
View file

@ -3080,6 +3080,20 @@
drive-strength = <2>;
};
};
usb3phy_portselect_gpio: usb3phy_portselect_gpio {
mux {
pins = "gpio81";
function = "gpio";
};
config {
pins = "gpio81";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
};
bt_en_sleep: bt_en_sleep {

48
qcom/shima-qrd.dtsi
View file

@ -78,7 +78,7 @@
vdd-io-supply = <&L6C>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
qcom,vdd-io-current-level = <0 30000>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};
@ -293,10 +293,10 @@
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0222>;
<&wsa883x_0222>, <&ext_disp_audio_codec>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd938x_codec", "swr-haptics",
"wsa-codec2";
"wsa-codec2", "msm-ext-disp-audio-codec-rx";
qcom,wsa-max-devs = <1>;
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
@ -310,3 +310,45 @@
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
};
&usb0 {
ssusb_redriver = <&redriver>;
};
&usb_qmp_dp_phy {
pinctrl-names = "portselect";
};
&qupv3_se5_i2c {
status = "ok"
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
pinctrl-names = "enable_gpio";
pinctrl-0 = <&usb3phy_portselect_gpio>;
orientation_gpio = <&tlmm 81 0>;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x6 0x4 0x4 0x6>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x2 0x1 0x1 0x2>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};

7
qcom/shima-qupv3.dtsi
View file

@ -53,7 +53,8 @@
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0xff>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x7e>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
qcom,gpi-ee-offset = <0x10000>;
@ -174,8 +175,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
dmas = <&gpi_dma0 0 2 3 64 0>,
<&gpi_dma0 1 2 3 64 0>;
dmas = <&gpi_dma0 0 2 3 64 2>,
<&gpi_dma0 1 2 3 64 2>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";

67
qcom/shima-vm.dtsi
View file

@ -1,4 +1,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-shima.h>
#include <dt-bindings/clock/qcom,gcc-shima.h>
#include <dt-bindings/clock/qcom,rpmh.h>
/ {
#address-cells = <0x2>;
@ -224,5 +227,69 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/*
* QUPv3 Instances
* Qup0 2: SE 10
*/
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9c0000 0x2000>;
};
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,gpii-mask = <0x80>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;
status = "ok"
};
/* I2C SE */
qupv3_se10_i2c: i2c@988000 {
compatible = "qcom,i2c-geni";
reg = <0x988000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma0 0 2 3 64 0>,
<&gpi_dma0 1 2 3 64 0>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "ok"
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};
};
#include "lahaina-vm-ion.dtsi"
#include "display/trustedvm-shima-sde.dtsi"
#include "display/trustedvm-shima-sde-display.dtsi"

67
qcom/shima.dtsi
View file

@ -469,6 +469,14 @@
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_memory";
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
};
chosen {
@ -1707,7 +1715,14 @@
dma-coherent;
rpm-level = <3>;
spm-level = <5>;
/*
* Hynix UFS2.2 is drawing 40mA current during APPS PC.
* Issue is seen only if PX10 is turned off and Vccq2 is ON.
* Since Vccq2 is always-on supply we can't turn it off,
* so don't turn off PX10, by updating spm_lvl to 3.
* In sleep state (spm-lvl=3) its drawing only .5mA.
*/
spm-level = <3>;
status = "disabled";
@ -2189,13 +2204,13 @@
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */
BW_OPP_ENTRY( 300, 32); /* 9155 MB/s */
BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */
BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */
BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */
BW_OPP_ENTRY( 933, 32); /* 28472 MB/s */
BW_OPP_ENTRY( 1066, 32); /* 30516 MB/s */
BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
BW_OPP_ENTRY( 1066, 16); /* 15258 MB/s */
};
ddr_bw_opp_table: ddr-bw-opp-table {
@ -2523,9 +2538,9 @@
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 1171200 MHZ_TO_MBPS( 300, 32) >,
< 1516800 MHZ_TO_MBPS( 466, 32) >,
< 1804800 MHZ_TO_MBPS( 600, 32) >;
< 1171200 MHZ_TO_MBPS( 300, 16) >,
< 1516800 MHZ_TO_MBPS( 466, 16) >,
< 1804800 MHZ_TO_MBPS( 600, 16) >;
};
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
@ -2571,12 +2586,12 @@
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 300, 32) >,
< 940800 MHZ_TO_MBPS( 466, 32) >,
< 1209600 MHZ_TO_MBPS( 600, 32) >,
< 1651800 MHZ_TO_MBPS( 806, 32) >,
< 2361600 MHZ_TO_MBPS( 933, 32) >,
< 2707200 MHZ_TO_MBPS( 1066, 32) >;
< 691000 MHZ_TO_MBPS( 300, 16) >,
< 940800 MHZ_TO_MBPS( 466, 16) >,
< 1209600 MHZ_TO_MBPS( 600, 16) >,
< 1651800 MHZ_TO_MBPS( 806, 16) >,
< 2361600 MHZ_TO_MBPS( 933, 16) >,
< 2707200 MHZ_TO_MBPS( 1066, 16) >;
};
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
@ -2662,8 +2677,8 @@
qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,core-dev-table =
< 1900800 MHZ_TO_MBPS( 150, 32) >,
< 2707200 MHZ_TO_MBPS( 600, 32) >;
< 1900800 MHZ_TO_MBPS( 150, 16) >,
< 2707200 MHZ_TO_MBPS( 600, 16) >;
};
cpu7_computemon: qcom,cpu7-computemon {
@ -3890,7 +3905,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3900,7 +3914,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3909,7 +3922,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3918,7 +3930,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3927,7 +3938,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3937,7 +3947,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3947,7 +3956,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3956,7 +3964,6 @@
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3965,8 +3972,8 @@
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
vdd_parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};
@ -3975,7 +3982,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3984,7 +3990,6 @@
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3994,7 +3999,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4003,7 +4007,6 @@
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
vdd_parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};

39
qcom/smb1355.dtsi Normal file
View file

@ -0,0 +1,39 @@
#include <dt-bindings/interrupt-controller/irq.h>
smb1355: qcom,smb1355@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&spmi_bus>;
interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt_names = "smb1355";
interrupt-controller;
#interrupt-cells = <3>;
qcom,periph-map = <0x10 0x12 0x13 0x16>;
status = "disabled";
smb1355_charger: qcom,smb1355-charger@1000 {
compatible = "qcom,smb1355";
reg = <0x1000 0x700>;
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&smb1355>;
status = "disabled";
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chg-state-change";
};
qcom,chgr-misc@1600 {
reg = <0x1600 0x100>;
interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x16 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog-bark",
"temperature-change";
};
};
};

11
qcom/yupik-pinctrl.dtsi Normal file
View file

@ -0,0 +1,11 @@
&soc {
tlmm: pinctrl@f000000 {
compatible = "qcom,yupik-pinctrl";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

11
qcom/yupik-rumi-overlay.dts Normal file
View file

@ -0,0 +1,11 @@
/dts-v1/;
/plugin/;
#include "yupik-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Yupik RUMI";
compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi";
qcom,msm-id = <475 0x10000>;
qcom,board-id = <0x1000f 0>;
};

11
qcom/yupik-rumi.dts Normal file
View file

@ -0,0 +1,11 @@
/dts-v1/;
/memreserve/ 0x90000000 0x00000100;
#include "yupik.dtsi"
#include "yupik-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Yupik RUMI";
compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi";
qcom,board-id = <0x1000f 0>;
};

13
qcom/yupik-rumi.dtsi Normal file
View file

@ -0,0 +1,13 @@
&soc {
timer {
clock-frequency = <5000000>;
};
timer@17c20000 {
clock-frequency = <5000000>;
};
wdog: qcom,wdt@17c10000 {
status = "disabled";
};
};

471
qcom/yupik-stub-regulator.dtsi Normal file
View file

@ -0,0 +1,471 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
VDD_GFX_LEVEL:
S7C_LEVEL:
pm8350c_s7_level: regulator-pm8350c-s7-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s7_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S1B:
pm74xx_s1: regulator-pm74xx-s1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_s1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2040000>;
};
S2B:
pm74xx_s2: regulator-pm74xx-s2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_s2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1050000>;
};
S7B:
pm74xx_s7: regulator-pm74xx-s7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_s7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
};
S8B:
pm74xx_s8: regulator-pm74xx-s8 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_s8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1500000>;
};
L1B:
pm74xx_l1: regulator-pm74xx-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
};
L2B:
pm74xx_l2: regulator-pm74xx-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
VDD_IO_EBI_LEVEL:
L3B_LEVEL:
pm74xx_l3_level: regulator-pm74xx-l3-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l3_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_LPI_MX_LEVEL:
L4B_LEVEL:
pm74xx_l4_level: regulator-pm74xx-l4-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l4_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_LPI_CX_LEVEL:
L5B_LEVEL:
pm74xx_l5_level: regulator-pm74xx-l5-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l5_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L6B:
pm74xx_l6: regulator-pm74xx-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l6";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
};
L7B:
pm74xx_l7: regulator-pm74xx-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
};
L8B:
pm74xx_l8: regulator-pm74xx-l8 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
};
L9B:
pm74xx_l9: regulator-pm74xx-l9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L10B:
pm74xx_l10: regulator-pm74xx-l10 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l10";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1170000>;
regulator-max-microvolt = <1304000>;
};
L11B:
pm74xx_l11: regulator-pm74xx-l11 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l11";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L12B:
pm74xx_l12: regulator-pm74xx-l12 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l12";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
};
L13B:
pm74xx_l13: regulator-pm74xx-l13 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l13";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <824000>;
};
L14B:
pm74xx_l14: regulator-pm74xx-l14 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l14";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L15B:
pm74xx_l15: regulator-pm74xx-l15 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l15";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <765000>;
regulator-max-microvolt = <1020000>;
};
L16B:
pm74xx_l16: regulator-pm74xx-l16 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l16";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1139000>;
regulator-max-microvolt = <1236000>;
};
L17B:
pm74xx_l17: regulator-pm74xx-l17 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l17";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
L18B:
pm74xx_l18: regulator-pm74xx-l18 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l18";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
};
L19B:
pm74xx_l19: regulator-pm74xx-l19 {
compatible = "qcom,stub-regulator";
regulator-name = "pm74xx_l19";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
S1C:
pm8350c_s1: regulator-pm8350c-s1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2160000>;
regulator-max-microvolt = <2200000>;
};
VDD_MODEM_LEVEL:
S5C_LEVEL:
pm8350c_s5_level: regulator-pm8350c-s5-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s5_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL:
S2C_LEVEL:
pm8350c_s2_level: regulator-pm8350c-s2-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s2_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO:
S2C_LEVEL_AO:
pm8350c_s2_level_ao: regulator-pm8350c-s2-level-ao {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s2_level_ao";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S9C:
pm8350c_s9: regulator-pm8350c-s9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
VDD_MX_LEVEL:
S10C_LEVEL:
pm8350c_s10_level: regulator-pm8350c-s10-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s10_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MX_LEVEL_AO:
S10C_LEVEL_AO:
pm8350c_s10_level_ao: regulator-pm8350c-s10-level-ao {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_s10_level_ao";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L1C:
pm8350c_l1: regulator-pm8350c-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L2C:
pm8350c_l2: regulator-pm8350c-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L3C:
pm8350c_l3: regulator-pm8350c-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l3";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3544000>;
};
L4C:
pm8350c_l4: regulator-pm8350c-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l4";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L5C:
pm8350c_l5: regulator-pm8350c-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l5";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L6C:
pm8350c_l6: regulator-pm8350c-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l6";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
};
L7C:
pm8350c_l7: regulator-pm8350c-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3544000>;
};
L8C:
pm8350c_l8: regulator-pm8350c-l8 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
};
L9C:
pm8350c_l9: regulator-pm8350c-l9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L10C:
pm8350c_l10: regulator-pm8350c-l10 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l10";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
};
L11C:
pm8350c_l11: regulator-pm8350c-l11 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l11";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
};
L12C:
pm8350c_l12: regulator-pm8350c-l12 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l12";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L13C:
pm8350c_l13: regulator-pm8350c-l13 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_l13";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L1D:
pm8350b_l1: regulator-pm8350b-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350b_l1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
};
BOB:
pm8350c_bob: regulator-pm8350c-bob {
compatible = "qcom,stub-regulator";
regulator-name = "pm8350c_bob";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
};
L2E:
pmr735a_l2: regulator-pmr735a-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pmr735a_l2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
};
L3E:
pmr735a_l3: regulator-pmr735a-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pmr735a_l3";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <765000>;
regulator-max-microvolt = <1020000>;
};
L4E:
pmr735a_l4: regulator-pmr735a-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pmr735a_l4";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1615000>;
regulator-max-microvolt = <1890000>;
};
L5E:
pmr735a_l5: regulator-pmr735a-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pmr735a_l5";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <760000>;
regulator-max-microvolt = <840000>;
};
L6E:
pmr735a_l6: regulator-pmr735a-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pmr735a_l6";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <880000>;
};
};

9
qcom/yupik.dts Normal file
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@ -0,0 +1,9 @@
/dts-v1/;
#include "yupik.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Yupik SoC";
compatible = "qcom,yupik";
qcom,board-id = <0 0>;
};

685
qcom/yupik.dtsi Normal file
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@ -0,0 +1,685 @@
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-yupik.h>
#include <dt-bindings/clock/qcom,dispcc-yupik.h>
#include <dt-bindings/clock/qcom,gcc-yupik.h>
#include <dt-bindings/clock/qcom,gpucc-yupik.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-yupik.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,yupik.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
/ {
model = "Qualcomm Technologies, Inc. Yupik";
compatible = "qcom,yupik";
qcom,msm-id = <475 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
};
cluster2 {
core0 {
cpu = <&CPU7>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: cmd_db@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi: reserved_xbl_uefi@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
secdata_apss_mem: secdata_apss@808ff000 {
no-map;
reg = <0x0 0x808ff000 0x0 0x1000>;
};
smem_mem: smem@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
fw_mem: fw@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_fw_mem: wlan_fw@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0xc00000>;
};
cdsp_secure_heap_mem: cdsp_secure_heap@81800000 {
no-map;
reg = <0x0 0x81800000 0x0 0x1e00000>;
};
pil_cvp_mem: camera@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x500000>;
};
pil_adsp_mem: adsp@86700000 {
no-map;
reg = <0x0 0x86700000 0x0 0x2800000>;
};
pil_cdsp_mem: cdsp@88f00000 {
no-map;
reg = <0x0 0x88f00000 0x0 0x1e00000>;
};
pil_camera_mem: video@8ad00000 {
no-map;
reg = <0x0 0x8ad00000 0x0 0x500000>;
};
pil_video_mem: cvp@8b200000 {
no-map;
reg = <0x0 0x8b200000 0x0 0x500000>;
};
pil_ipa_fw_mem: ipa_fw@8b700000 {
no-map;
reg = <0x0 0x8b700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi@8b710000 {
no-map;
reg = <0x0 0x8b710000 0x0 0xa000>;
};
pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 {
no-map;
reg = <0x0 0x8b71a000 0x0 0x2000>;
};
pil_mpss_mem: mpss@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0xf600000>;
};
pil_wpss_mem: wlan@9ae00000 {
no-map;
reg = <0x0 0x9ae00000 0x0 0x1900000>;
};
removed_mem: removed_region@c0000000 {
no-map;
reg = <0x0 0xc0000000 0x0 0x5100000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
};
soc: soc { };
chosen { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie-0-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie-1-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
aopcc: qcom,aopcc {
compatible = "qcom,dummycc";
clock-output-names = "aopcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
rpmhcc: qcom,rpmhcc {
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,dummycc";
clock-output-names = "camcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,dummycc";
clock-output-names = "dispcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,dummycc";
clock-output-names = "videocc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
clk_virt: interconnect {
compatible = "qcom,yupik-clk_virt";
#interconnect-cells = <1>;
};
config_noc: interconnect@1500000 {
compatible = "qcom,yupik-config_noc";
#interconnect-cells = <1>;
};
mc_virt: interconnect@1580000 {
compatible = "qcom,yupik-mc_virt";
#interconnect-cells = <1>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,yupik-system_noc";
#interconnect-cells = <1>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,yupik-aggre1_noc";
#interconnect-cells = <1>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,yupik-aggre2_noc";
#interconnect-cells = <1>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,yupik-mmss_noc";
#interconnect-cells = <1>;
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,yupik-lpass_ag_noc";
#interconnect-cells = <1>;
};
dc_noc: interconnect@90e0000 {
compatible = "qcom,yupik-dc_noc";
#interconnect-cells = <1>;
};
gem_noc: interconnect@9100000 {
compatible = "qcom,yupik-gem_noc";
#interconnect-cells = <1>;
};
nsp_noc: interconnect@a0c0000 {
compatible = "qcom,yupik-nsp_noc";
#interconnect-cells = <1>;
};
epss_l3_cpu: l3_cpu@18590000 {
compatible = "qcom,yupik-epss-l3-cpu";
#interconnect-cells = <1>;
};
};
#include "shima-gdsc.dtsi"
#include "yupik-pinctrl.dtsi"
#include "yupik-stub-regulator.dtsi"
&gcc_pcie_0_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_pcie_1_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_ufs_phy_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_usb30_prim_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&gcc_usb30_sec_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&cam_cc_titan_top_gdsc {
compatible = "regulator-fixed";
reg = <0xad0c194 0x4>;
status = "ok"
};
&cam_cc_bps_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&cam_cc_ife_0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&cam_cc_ife_1_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&cam_cc_ife_2_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&cam_cc_ipe_0_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&disp_cc_mdss_core_gdsc {
compatible = "regulator-fixed";
reg = <0xaf01004 0x4>;
qcom,support-hw-trigger;
status = "ok"
};
&gpu_cx_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&gpu_gx_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&video_cc_mvs0_gdsc {
compatible = "regulator-fixed";
reg = <0xaaf3004 0x4>;
qcom,support-hw-trigger;
status = "ok"
};
&video_cc_mvsc_gdsc {
compatible = "regulator-fixed";
status = "ok"
};