A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Disable L1SS sleep for Lahaina

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Remove the software workaround to manually manage
the phy PLL. Keep the phy PLL on all the time by
disabling L1SS sleep. This is required to prevent
PCIe link down issue upon exiting the L1SS sleep.

Change-Id: I6251f05d1ae0572b958740460606e3eeb51c59ed
This commit is contained in:
Hemant Kumar 2020-07-01 10:49:17 -07:00
commit bdcff7e7b9
1 changed files with 1 additions and 5 deletions
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6
qcom/lahaina-pcie.dtsi
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@ -101,6 +101,7 @@
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,l1ss-sleep-disable = <0x1>;
qcom,drv-l1ss-timeout-us = <10000>;
qcom,use-19p2mhz-aux-clk;
qcom,no-l0s-supported;
@ -109,11 +110,6 @@
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,phy-manage-pll = <1>;
qcom,phy-resetsm-cntrl2 = <0xa0>;
qcom,phy-core-pll-en-mux = <7>;
qcom,phy-c-ready-status = <0x178>;
qcom,pcie-phy-ver = <10099>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;