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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add initial device tree for Yupik
Add initial device tree to support Yupik on RUMI platform. Change-Id: I5d2614ce33aeac276011fb4623be767ac412dde2
This commit is contained in:
Neeraj Upadhyay
Gerrit - the friendly Code Review server
parent
a14fb78642
commit
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7 changed files with 323 additions and 0 deletions
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@ -56,6 +56,9 @@ SoCs:
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- SHIMA
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compatible = "qcom,shima"
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- YUPIK
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compatible = "qcom,yupik"
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- LITO
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compatible = "qcom,lito"
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@ -206,6 +209,7 @@ compatible = "qcom,shima-rumi"
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compatible = "qcom,shima-idp"
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compatible = "qcom,shima-atp"
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compatible = "qcom,shima-qrd"
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compatible = "qcom,yupik-rumi"
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compatible = "qcom,lito-rumi"
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compatible = "qcom,lito-mtp"
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compatible = "qcom,lito-cdp"
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@ -122,6 +122,15 @@ dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \
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shima-idps-digital-mics.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_YUPIK) += \
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yupik-rumi-overlay.dtbo
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yupik-rumi-overlay.dtbo-base := yupik.dtb
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else
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dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_SM8150) += \
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sm8150-cdp-overlay.dtbo \
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11
qcom/yupik-rumi-overlay.dts
Normal file
11
qcom/yupik-rumi-overlay.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "yupik-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik RUMI";
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compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi";
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qcom,msm-id = <475 0x10000>;
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qcom,board-id = <0x1000f 0>;
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};
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11
qcom/yupik-rumi.dts
Normal file
11
qcom/yupik-rumi.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x90000000 0x00000100;
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#include "yupik.dtsi"
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#include "yupik-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik RUMI";
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compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi";
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qcom,board-id = <0x1000f 0>;
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};
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13
qcom/yupik-rumi.dtsi
Normal file
13
qcom/yupik-rumi.dtsi
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@ -0,0 +1,13 @@
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&soc {
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timer {
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clock-frequency = <5000000>;
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};
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timer@17c20000 {
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clock-frequency = <5000000>;
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};
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wdog: qcom,wdt@17c10000 {
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status = "disabled";
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};
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};
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9
qcom/yupik.dts
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9
qcom/yupik.dts
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@ -0,0 +1,9 @@
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/dts-v1/;
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#include "yupik.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik SoC";
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compatible = "qcom,yupik";
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qcom,board-id = <0 0>;
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};
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266
qcom/yupik.dtsi
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266
qcom/yupik.dtsi
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@ -0,0 +1,266 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Yupik";
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compatible = "qcom,yupik";
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qcom,msm-id = <475 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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chosen { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c29000 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2b000 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2d000 0x1000>;
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status = "disabled";
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};
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};
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};
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