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ARM: dts: msm: Add support to pass MSI address size on Lahaina

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Some targets need to set the MSI address size same as the
PCIe data size(bytes) that PCIe core will halt for each write
transaction. Hence add a property to pass the exponent (base 2)
value for the size. Not setting this value same as PCIe core
write halt size results into a deadlock on system bus.

Change-Id: I9d8dd27fdb7ee25d5673a0fc96bf43f0aa6013ab
This commit is contained in:
Hemant Kumar 2020-07-16 13:23:16 -07:00
commit c25fdafc00
1 changed files with 1 additions and 0 deletions
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1
qcom/lahaina-pcie.dtsi
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@ -200,6 +200,7 @@
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17a10040 0x0>;
qcom,msi-addr-size-exp = <20>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,