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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "msm: pcie: add sysfs entry to output PCIe link ASPM stats"
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commit
c63c285927
1 changed files with 41 additions and 0 deletions
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@ -83,6 +83,11 @@
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#define PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS (0x630)
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#define PCIE20_PARF_STATUS (0x230)
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#define PCIE20_PARF_DEBUG_CNT_IN_L0S (0xc10)
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#define PCIE20_PARF_DEBUG_CNT_IN_L1 (0xc0c)
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#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1 (0xc84)
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#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2 (0xc88)
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#define PCIE20_PARF_CLKREQ_OVERRIDE (0x2b0)
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#define PCIE20_PARF_CLKREQ_IN_VALUE (BIT(3))
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#define PCIE20_PARF_CLKREQ_IN_ENABLE (BIT(1))
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@ -332,6 +337,7 @@ enum msm_pcie_res {
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MSM_PCIE_RES_ELBI,
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MSM_PCIE_RES_IATU,
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MSM_PCIE_RES_CONF,
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MSM_PCIE_RES_MHI,
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MSM_PCIE_RES_TCSR,
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MSM_PCIE_RES_RUMI,
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MSM_PCIE_MAX_RES,
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@ -710,6 +716,7 @@ struct msm_pcie_dev_t {
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void __iomem *iatu;
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void __iomem *dm_core;
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void __iomem *conf;
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void __iomem *mhi;
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void __iomem *tcsr;
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void __iomem *rumi;
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@ -1063,6 +1070,7 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = {
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{"elbi", NULL, NULL},
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{"iatu", NULL, NULL},
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{"conf", NULL, NULL},
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{"mhi", NULL, NULL},
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{"tcsr", NULL, NULL},
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{"rumi", NULL, NULL}
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};
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@ -2133,6 +2141,36 @@ static ssize_t enumerate_store(struct device *dev,
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}
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static DEVICE_ATTR_WO(enumerate);
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static ssize_t aspm_stat_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct msm_pcie_dev_t *pcie_dev = dev_get_drvdata(dev);
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if (!pcie_dev->mhi)
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return scnprintf(buf, PAGE_SIZE,
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"PCIe: RC%d: No dev or MHI space found\n",
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pcie_dev->rc_idx);
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if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED)
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return scnprintf(buf, PAGE_SIZE,
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"PCIe: RC%d: registers are not accessible\n",
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pcie_dev->rc_idx);
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return scnprintf(buf, PAGE_SIZE,
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"PCIe: RC%d: L0s: %u L1: %u L1.1: %u L1.2: %u\n",
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pcie_dev->rc_idx,
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readl_relaxed(pcie_dev->mhi +
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PCIE20_PARF_DEBUG_CNT_IN_L0S),
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readl_relaxed(pcie_dev->mhi +
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PCIE20_PARF_DEBUG_CNT_IN_L1),
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readl_relaxed(pcie_dev->mhi +
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PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1),
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readl_relaxed(pcie_dev->mhi +
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PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2));
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}
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static DEVICE_ATTR_RO(aspm_stat);
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static ssize_t l23_rdy_poll_timeout_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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@ -2167,6 +2205,7 @@ static DEVICE_ATTR_RW(l23_rdy_poll_timeout);
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static struct attribute *msm_pcie_debug_attrs[] = {
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&dev_attr_link_check_max_count.attr,
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&dev_attr_enumerate.attr,
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&dev_attr_aspm_stat.attr,
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&dev_attr_l23_rdy_poll_timeout.attr,
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NULL,
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};
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@ -4066,6 +4105,7 @@ static int msm_pcie_get_reg(struct msm_pcie_dev_t *pcie_dev)
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pcie_dev->iatu = pcie_dev->res[MSM_PCIE_RES_IATU].base;
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pcie_dev->dm_core = pcie_dev->res[MSM_PCIE_RES_DM_CORE].base;
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pcie_dev->conf = pcie_dev->res[MSM_PCIE_RES_CONF].base;
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pcie_dev->mhi = pcie_dev->res[MSM_PCIE_RES_MHI].base;
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pcie_dev->tcsr = pcie_dev->res[MSM_PCIE_RES_TCSR].base;
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pcie_dev->rumi = pcie_dev->res[MSM_PCIE_RES_RUMI].base;
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@ -4182,6 +4222,7 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev)
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dev->iatu = NULL;
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dev->dm_core = NULL;
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dev->conf = NULL;
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dev->mhi = NULL;
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dev->tcsr = NULL;
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dev->rumi = NULL;
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}
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