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msm: kgsl: Enable HWCG after a6xx register configurations

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For A6xx GPU enable hardware clock gating after register
configuration to avoid register access issue due to hardware
internal clock gating.

Change-Id: If55632ccf9171a7093bb1e925e4fcdb88066417c
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
This commit is contained in:
Hareesh Gundu 2020-08-19 16:40:50 +05:30 • committed by Gerrit - the friendly Code Review server
commit c86af5a851
1 changed files with 6 additions and 3 deletions
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9
drivers/gpu/msm/adreno_a6xx.c
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@ -423,9 +423,6 @@ void a6xx_start(struct adreno_device *adreno_dev)
unsigned int rgb565_predicator = 0;
static bool patch_reglist;
/* enable hardware clockgating */
a6xx_hwcg_set(adreno_dev, true);
/* Enable 64 bit addressing */
kgsl_regwrite(device, A6XX_CP_ADDR_MODE_CNTL, 0x1);
kgsl_regwrite(device, A6XX_VSC_ADDR_MODE_CNTL, 0x1);
@ -657,6 +654,12 @@ void a6xx_start(struct adreno_device *adreno_dev)
a6xx_set_secvid(device);
/*
* Enable hardware clock gating here to prevent any register access
* issue due to internal clock gating.
*/
a6xx_hwcg_set(adreno_dev, true);
/*
* All registers must be written before this point so that we don't
* miss any register programming when we patch the power up register