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ARM: dts: msm: Add device node for llcc node on SDMSHRIKE

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Add device node for last level cache controller on
SDMSHRIKE target.

Change-Id: I33ef1895e9228cf897942051eb1f7fd7596d79a1
This commit is contained in:
Shreyas K K 2021-01-05 20:10:48 +05:30
commit c97537f9ec
2 changed files with 8 additions and 0 deletions
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1
bindings/arm/msm/qcom,llcc.txt
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@ -14,6 +14,7 @@ Properties:
Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
or "qcom,yupik-llcc" or "qcom,sm8150-llcc"
or "qcom,sdmshrike-llcc"
"qcom,llcc-v2" must be appended for V2 hardware.
- reg:

7
qcom/sdmshrike.dtsi
View file

@ -621,6 +621,13 @@
};
};
cache-controller@9200000 {
compatible = "qcom,sdmshrike-llcc";
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;