Merge "ARM: dts: msm: add DCC register list for sdxlemur"

This commit is contained in:
qctecmdr 2021-01-08 04:04:49 -08:00 • committed by Gerrit - the friendly Code Review server
commit ca287bde87

View file

@ -199,6 +199,15 @@
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
link_list1 {
qcom,curr-link-list = <2>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0xb204520 1 0>,
<DCC_READ 0xb201020 1 0>,
<DCC_READ 0xb201024 1 0>,
<DCC_READ 0xb204524 1 0>;
};
};
wdog: qcom,wdt@17817000 {