A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-11 07:03:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

dlkm: add enable CP api

Browse source 
add enable CP api for ESR.
disable all CP before ESR and switch to PMIC
enable all CP after ESR

Change-Id: If7b2a60eec763f578b81ecd65844f79d3fa94044
Signed-off-by: Haijian Ma <mahj8@motorola.com>
Reviewed-on: https://gerrit.mot.com/1526649
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Wentao Xu <xuwt2@motorola.com>
Reviewed-by: Lu Chai <chailu1@motorola.com>
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
Reviewed-on: https://gerrit.mot.com/1893604
Reviewed-by: Wei Xu <xuwei9@lenovo.com>
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
This commit is contained in:
Haijian Ma 2020-04-02 16:07:24 +08:00 • committed by Wei Xu
commit ccfde9622d
4 changed files with 52 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

11
drivers/power/mmi_parallel_charger/mmi_charger_core.c
View file

@ -600,6 +600,7 @@ static enum power_supply_property mmi_chrg_mgr_props[] = {
POWER_SUPPLY_PROP_CHARGE_COUNTER,
POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL,
POWER_SUPPLY_PROP_NUM_SYSTEM_TEMP_LEVELS,
POWER_SUPPLY_PROP_CP_ENABLE,
};
static int mmi_chrg_mgr_get_property(struct power_supply *psy,
@ -657,6 +658,9 @@ static int mmi_chrg_mgr_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_NUM_SYSTEM_TEMP_LEVELS:
val->intval = chip->thermal_levels;
break;
case POWER_SUPPLY_PROP_CP_ENABLE:
val->intval = !chip->cp_disable;
break;
default:
return -EINVAL;
@ -695,7 +699,11 @@ static int mmi_chrg_mgr_set_property(struct power_supply *psy,
return -EINVAL;
chip->pd_volt_max= val->intval;
break;
case POWER_SUPPLY_PROP_CP_ENABLE:
if (chip->pd_pps_support
&& !chip->factory_mode)
mmi_chrg_enable_all_cp(chip, val->intval);
break;
default:
return -EINVAL;
}
@ -712,6 +720,7 @@ static int mmi_chrg_mgr_is_writeable(struct power_supply *psy,
case POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL:
case POWER_SUPPLY_PROP_PD_CURRENT_MAX:
case POWER_SUPPLY_PROP_PD_VOLTAGE_MAX:
case POWER_SUPPLY_PROP_CP_ENABLE:
ret = 1;
break;
default:

1
drivers/power/mmi_parallel_charger/mmi_charger_core.h
View file

@ -153,6 +153,7 @@ struct mmi_charger_manager {
bool factory_mode;
bool suspended;
bool awake;
bool cp_disable;
int *debug_mask;
int mmi_pd_pdo_idx; /*request the pdo idx of PD*/

1
drivers/power/mmi_parallel_charger/mmi_charger_policy.h
View file

@ -31,4 +31,5 @@ extern int mmi_chrg_policy_init(struct mmi_charger_manager *chip,
struct mmi_chrg_dts_info *chrg_dts,
int chrg_cnt);
extern void mmi_chrg_policy_clear(struct mmi_charger_manager *chip);
extern void mmi_chrg_enable_all_cp(struct mmi_charger_manager *chip, int val);
#endif

40
drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c
View file

@ -273,6 +273,45 @@ static void chrg_policy_error_recovery(struct mmi_charger_manager *chip,
return;
}
void mmi_chrg_enable_all_cp(struct mmi_charger_manager *chip, int val)
{
struct mmi_cp_policy_dev *chrg_list = &g_chrg_list;
bool enable = !!val;
mmi_chrg_dbg(chip, PR_MOTO,"enable all cp = %d\n", enable);
if (enable) {
if (chip->cp_disable == false)
return;
cancel_delayed_work_sync(&chip->mmi_chrg_sm_work);
mmi_chrg_sm_move_state(chip, PM_STATE_CHRG_PUMP_ENTRY);
chip->cp_disable = false;
schedule_delayed_work(&chip->mmi_chrg_sm_work,
msecs_to_jiffies(0));
} else {
if(chrg_list->cp_master
&& !chrg_list->chrg_dev[CP_MASTER]->charger_enabled)
return;
cancel_delayed_work_sync(&chip->mmi_chrg_sm_work);
chip->cp_disable = true;
if (chrg_list->cp_slave
&& chrg_list->chrg_dev[CP_SLAVE]->charger_enabled) {
mmi_enable_charging(chrg_list->chrg_dev[CP_SLAVE], false);
}
if (chrg_list->cp_master
&& chrg_list->chrg_dev[CP_MASTER]->charger_enabled) {
mmi_enable_charging(chrg_list->chrg_dev[CP_MASTER], false);
}
mmi_chrg_sm_move_state(chip, PM_STATE_RECOVERY_SW);
schedule_delayed_work(&chip->mmi_chrg_sm_work,
msecs_to_jiffies(0));
}
}
#define HEARTBEAT_SHORT_DELAY_MS 1000
#define HEARTBEAT_lOOP_WAIT_MS 3000
@ -611,6 +650,7 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
break;
case PM_STATE_SW_LOOP:
if (chip->pd_pps_support
&& chip->cp_disable == false
&& vbatt_volt > chip->pl_chrg_vbatt_min
&& chrg_step->pres_chrg_step != chip->chrg_step_nums - 1
&& chrg_step->chrg_step_cc_curr >=