mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
Merge "ARM: dts: msm: Add QDSS devictree for sdxnightjar"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
cd0eebfb6a
2 changed files with 611 additions and 2 deletions
608
qcom/sdxnightjar-coresight.dtsi
Normal file
608
qcom/sdxnightjar-coresight.dtsi
Normal file
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@ -0,0 +1,608 @@
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&soc {
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fuse: fuse@a601c {
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compatible = "arm,coresight-fuse-v2";
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reg = <0xa601c 0x8>,
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<0xa600c 0x4>;
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reg-names = "fuse-base", "qpdi-fuse-base";
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coresight-name = "coresight-fuse";
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};
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csr: csr@801000 {
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compatible = "qcom,coresight-csr";
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reg = <0x801000 0x1000>;
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reg-names = "csr-base";
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coresight-name = "coresight-csr";
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qcom,usb-bam-support;
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qcom,hwctrl-set-support;
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qcom,set-byte-cntr-support;
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qcom,blk-size = <1>;
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};
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hwevent {
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compatible = "qcom,coresight-hwevent";
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coresight-name = "coresight-hwevent";
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coresight-csr = <&csr>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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};
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stm: stm@802000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb962>;
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reg = <0x802000 0x1000>,
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<0x9280000 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-stm";
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out-ports {
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port {
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stm_out_funnel_in0: endpoint {
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remote-endpoint = <&funnel_in0_in_stm>;
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};
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};
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};
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};
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dbgui: dbgui@86d000 {
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compatible = "qcom,coresight-dbgui";
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reg = <0x86d000 0x1000>;
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reg-names = "dbgui-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-dbgui";
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qcom,dbgui-addr-offset = <0x30>;
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qcom,dbgui-data-offset = <0xb0>;
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qcom,dbgui-size = <0x20>;
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out-ports {
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port {
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dbgui_out_funnel_in0: endpoint {
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remote-endpoint = <&funnel_in0_in_dbugi>;
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};
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};
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};
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};
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etm0: etm@842000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb956>;
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reg = <0x842000 0x1000>;
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cpu = <&CPU0>;
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qcom,tupwr-disable;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-etm0";
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out-ports {
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port {
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etm0_out_funnel_in1: endpoint {
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remote-endpoint = <&funnel_in1_in_etm0>;
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};
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};
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};
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};
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tpdm_modem: tpdm@83a000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb968>;
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reg = <0x83a000 0x1000>;
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reg-names = "tpdm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-tpdm-modem";
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out-ports {
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port {
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tpdm_modem_out_tpda_modem: endpoint {
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remote-endpoint =
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<&tpda_modem_in_tpdm_modem>;
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};
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};
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};
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};
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modem_etm0: modem_etm0 {
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compatible = "qcom,coresight-remote-etm";
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coresight-name = "coresight-modem-etm0";
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qcom,inst-id = <2>;
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out-ports {
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port {
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modem_etm0_out_funnel_in1: endpoint {
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remote-endpoint =
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<&funnel_in1_in_modem_etm0>;
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};
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};
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};
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};
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rpm_etm0: rpm_etm0 {
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compatible = "qcom,coresight-remote-etm";
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coresight-name = "coresight-rpm-etm0";
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qcom,inst-id = <4>;
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out-ports {
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port {
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rpm_etm0_out_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_in_rpm_etm0>;
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};
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};
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};
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};
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tpdm_dcc: tpdm@864000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb969>;
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reg = <0x864000 0x1000>;
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reg-names = "tpdm-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-tpdm-dcc";
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qcom,hw-enable-check;
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out-ports {
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port {
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tpdm_dcc_out_tpda: endpoint {
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remote-endpoint =
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<&tpda_in_tpdm_dcc>;
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};
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};
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};
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};
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tpda_modem: tpda@83b000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb969>;
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reg = <0x083b000 0x1000>;
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reg-names = "tpda-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-tpda-modem";
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qcom,tpda-atid = <67>;
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qcom,dsb-elem-size = <0 32>;
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qcom,cmb-elem-size = <0 8>;
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out-ports {
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port {
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tpda_modem_out_funnel_in1: endpoint {
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remote-endpoint =
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<&funnel_in1_in_tpda_modem>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpda_modem_in_tpdm_modem: endpoint {
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remote-endpoint =
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<&tpdm_modem_out_tpda_modem>;
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};
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};
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};
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};
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tpda: tpda@803000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb969>;
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reg = <0x0803000 0x1000>;
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reg-names = "tpda-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-tpda";
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qcom,tpda-atid = <65>;
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qcom,cmb-elem-size = <0 8>;
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out-ports {
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port {
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tpda_out_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_in_tpda>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpda_in_tpdm_dcc: endpoint {
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remote-endpoint =
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<&tpdm_dcc_out_tpda>;
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};
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};
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};
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};
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funnel_in0: funnel@821000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb908>;
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reg = <0x0821000 0x1000>;
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reg-names = "funnel-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-funnel-in0";
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out-ports {
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port {
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funnel_in0_out_funnel_merge: endpoint {
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remote-endpoint =
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<&funnel_merge_in_funnel_in0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_in0_in_rpm_etm0: endpoint {
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remote-endpoint =
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<&rpm_etm0_out_funnel_in0>;
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};
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};
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port@4 {
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reg = <4>;
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funnel_in0_in_dbugi: endpoint {
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remote-endpoint =
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<&dbgui_out_funnel_in0>;
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};
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};
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port@6 {
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reg = <6>;
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funnel_in0_in_tpda: endpoint {
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remote-endpoint =
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<&tpda_out_funnel_in0>;
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};
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};
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port@7 {
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reg = <7>;
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funnel_in0_in_stm: endpoint {
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remote-endpoint =
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<&stm_out_funnel_in0>;
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};
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};
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};
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};
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funnel_in1: funnel@822000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb908>;
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reg = <0x0822000 0x1000>;
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reg-names = "funnel-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-funnel-in1";
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out-ports {
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port {
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funnel_in1_out_funnel_merge: endpoint {
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remote-endpoint =
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<&funnel_merge_in_funnel_in1>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_in1_in_modem_etm0: endpoint {
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remote-endpoint =
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<&modem_etm0_out_funnel_in1>;
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};
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};
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port@5 {
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reg = <5>;
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funnel_in1_in_tpda_modem: endpoint {
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remote-endpoint =
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<&tpda_modem_out_funnel_in1>;
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||||
};
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||||
};
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port@7 {
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reg = <7>;
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funnel_in1_in_etm0: endpoint {
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remote-endpoint =
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<&etm0_out_funnel_in1>;
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};
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};
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};
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};
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funnel_merg: funnel@825000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x000bb908>;
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reg = <0x0825000 0x1000>;
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reg-names = "funnel-base";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
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clock-names = "apb_pclk";
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coresight-name = "coresight-funnel-merg";
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out-ports {
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port {
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funnel_merge_out_tmc_etf: endpoint {
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remote-endpoint =
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<&tmc_etf_in_funnel_merge>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel_merge_in_funnel_in0: endpoint {
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remote-endpoint =
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<&funnel_in0_out_funnel_merge>;
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||||
};
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||||
};
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port@1 {
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reg = <1>;
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funnel_merge_in_funnel_in1: endpoint {
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remote-endpoint =
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<&funnel_in1_out_funnel_merge>;
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||||
};
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||||
};
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||||
|
||||
};
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||||
};
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||||
|
||||
tmc_etf: tmc@827000 {
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compatible = "arm,primecell";
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||||
arm,primecell-periphid = <0x000bb961>;
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reg = <0x0827000 0x1000>;
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||||
reg-names = "tmc-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
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||||
coresight-name = "coresight-tmc-etf";
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coresight-ctis = <&cti0 &cti6>;
|
||||
cti-reset-trig-num = <0>;
|
||||
cti-flush-trig-num = <1>;
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
tmc_etf_in_funnel_merge: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_merge_out_tmc_etf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port {
|
||||
tmc_etf_out_replicator_qdss: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_qdss_in_tmc_etf>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
replicator_qdss: replicator@8026000 {
|
||||
compatible = "arm,coresight-dynamic-replicator",
|
||||
"arm,primecell";
|
||||
reg = <0x0826000 0x1000>;
|
||||
reg-names = "replicator-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-replicator-qdss";
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_qdss_in_tmc_etf: endpoint {
|
||||
remote-endpoint =
|
||||
<&tmc_etf_out_replicator_qdss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_qdss_out_tmc_etr: endpoint {
|
||||
remote-endpoint =
|
||||
<&tmc_etr_in_replicator_qdss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tmc_etr: tmc@828000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb961>;
|
||||
reg = <0x0828000 0x1000>,
|
||||
<0x884000 0x15000>;
|
||||
reg-names = "tmc-base", "bam-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-tmc-etr";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges;
|
||||
arm,buffer-size = <0x100000>;
|
||||
arm,scatter-gather;
|
||||
|
||||
coresight-ctis = <&cti0 &cti6>;
|
||||
cti-reset-trig-num = <0>;
|
||||
cti-flush-trig-num = <1>;
|
||||
coresight-csr = <&csr>;
|
||||
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "byte-cntr-irq";
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
tmc_etr_in_replicator_qdss: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_qdss_out_tmc_etr>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
cti0: cti@810000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x810000 0x1000>;
|
||||
|
||||
reg-names = "cti-base";
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti0";
|
||||
|
||||
};
|
||||
|
||||
cti1: cti@811000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x811000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti1";
|
||||
|
||||
};
|
||||
|
||||
cti2: cti@812000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x812000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti2";
|
||||
};
|
||||
|
||||
cti3: cti@813000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x813000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti3";
|
||||
};
|
||||
|
||||
cti4: cti@814000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x814000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti4";
|
||||
};
|
||||
|
||||
cti5: cti@815000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x815000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti5";
|
||||
};
|
||||
|
||||
cti6: cti@816000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x816000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti6";
|
||||
|
||||
};
|
||||
|
||||
cti_modem_cpu0: cti@8390000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x839000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti-modem-cpu0";
|
||||
};
|
||||
|
||||
cti_pmu_cpu0: cti@841000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x841000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti-pmu-cpu0";
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
cti_cpu0: cti@843000 {
|
||||
compatible = "arm,primecell";
|
||||
arm,primecell-periphid = <0x000bb966>;
|
||||
reg = <0x843000 0x1000>;
|
||||
reg-names = "cti-base";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
coresight-name = "coresight-cti-cpu0";
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -429,9 +429,9 @@
|
|||
reg-names = "etm-base","debug-base";
|
||||
|
||||
qcom,coresight-jtagmm-cpu = <&CPU0>;
|
||||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core_clk", "core_a_clk";
|
||||
};
|
||||
|
||||
tcsr_mutex_regs: syscon@1905000 {
|
||||
|
|
@ -809,5 +809,6 @@
|
|||
#include "pmd9650-rpm-regulator.dtsi"
|
||||
#include "sdxnightjar-regulator.dtsi"
|
||||
#include "sdxnightjar-usb.dtsi"
|
||||
#include "sdxnightjar-coresight.dtsi"
|
||||
#include "sdxnightjar-pinctrl.dtsi"
|
||||
#include "sdxnightjar-blsp.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue