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android_kernel_motorola_sm6375/qcom/sdxnightjar.dtsi

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#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sdxnightjar.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sdxnightjar.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
/ {
model = "Qualcomm Technologies, Inc. SDXNIGHTJAR";
compatible = "qcom,sdxnightjar";
qcom,msm-id = <484 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <0x1>;
#size-cells = <0x1>;
chosen { };
memory {
device_type = "memory";
reg = <0 0>;
};
reserved_memory: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
peripheral1_mem: peripheral1_region@0x87800000 {
no-map;
reg = <0x87800000 0x400000>;
label = "peripheral1_mem";
};
peripheral2_mem: peripheral2_region@0x87d00000 {
no-map;
reg = <0x87d00000 0x100000>;
label = "peripheral2_mem";
};
smem_mem: smem_region@0x87e80000 {
no-map;
reg = <0x87e80000 0xc0000>;
label = "smem_mem";
};
mss_mem: mss_region@0x88000000 {
no-map;
reg = <0x88000000 0x7300000>;
label = "mss_mem";
};
};
aliases { };
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
};
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
qcom,mpm2-sleep-counter@4a3000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x004a3000 0x1000>;
clock-frequency = <32768>;
};
qcom,msm-imem@8600000 {
compatible = "qcom,msm-imem";
reg = <0x8600000 0x1000>; /* Address and size of IMEM */
ranges = <0x0 0x8600000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
clock-output-names = "chip_sleep_clk";
#clock-cells = <0>;
};
};
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-sdxnightjar";
#clock-cells = <1>;
};
gcc: qcom,gcc@1800000 {
compatible = "qcom,sdxnightjar-gcc", "syscon";
reg = <0x1800000 0x80000>;
reg-names = "cc_base";
vdd_cx-supply = <&pmd9650_s5_level>;
vdd_cx_ao-supply = <&pmd9650_s5_level_ao>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>;
clock-names = "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>;
#reset-cells = <1>;
};
debugcc: qcom,cc-debug@1874000 {
compatible = "qcom,sdxnightjar-debugcc";
qcom,gcc = <&gcc>;
clock-names = "xo_clk_src";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
#clock-cells = <1>;
};
gdsc_usb30: qcom,gdsc@fc401e84 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_usb30";
reg = <0x185e078 0x4>;
};
gdsc_pcie: qcom,gdsc@0xfc401e18 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_pcie";
reg = <0x0185d044 0x4>;
};
qcom,msm-cpufreq {
compatible = "qcom,msm-cpufreq";
/*TODO: Fix the clock when tree is available*/
clock-names = "cpu0_clk", "cpu1_clk",
"cpu2_clk", "cpu3_clk";
qcom,cpufreq-table =
< 200000 >,
< 300000 >,
< 384000 >,
< 600000 >,
< 787200 >,
< 998400 >,
< 1190400 >,
< 1286400 >;
};
ahb_clk: qcom,ahb-clk-src {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
/*TODO: Fix the clock when tree is available*/
governor = "powersave";
freq-tbl-khz =
< 19200 >,
< 50000 >,
< 100000 >,
< 133330 >;
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>,
<0x0193d100 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
timer@b020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xb020000 0x1000>;
clock-frequency = <19200000>;
frame@b021000 {
frame-number = <0>;
interrupts = <0 7 0x4>,
<0 6 0x4>;
reg = <0xb021000 0x1000>,
<0xb022000 0x1000>;
};
frame@b023000 {
frame-number = <1>;
interrupts = <0 8 0x4>;
reg = <0xb023000 0x1000>;
status = "disabled";
};
frame@b024000 {
frame-number = <2>;
interrupts = <0 9 0x4>;
reg = <0xb024000 0x1000>;
status = "disabled";
};
frame@b025000 {
frame-number = <3>;
interrupts = <0 10 0x4>;
reg = <0xb025000 0x1000>;
status = "disabled";
};
frame@b026000 {
frame-number = <4>;
interrupts = <0 11 0x4>;
reg = <0xb026000 0x1000>;
status = "disabled";
};
frame@b027000 {
frame-number = <5>;
interrupts = <0 12 0x4>;
reg = <0xb027000 0x1000>;
status = "disabled";
};
frame@b028000 {
frame-number = <6>;
interrupts = <0 13 0x4>;
reg = <0xb028000 0x1000>;
status = "disabled";
};
frame@b029000 {
frame-number = <7>;
interrupts = <0 14 0x4>;
reg = <0xb029000 0x1000>;
status = "disabled";
};
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom_rng: qrng@e3000 {
compatible = "qcom,msm-rng";
reg = <0xe3000 0x1000>;
qcom,msm-rng-iface-clk;
qcom,no-qrng-config;
qcom,msm-bus,name = "msm-rng-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 618 0 0>, /* No vote */
<1 618 0 800>; /* 100 MB/s */
/*TODO: Fix the clock when tree is available*/
clock-names = "iface_clk";
};
qcom_tzlog: tz-log@08600720 {
compatible = "qcom,tz-log";
reg = <0x08600720 0x2000>;
};
qcom,qcedev@720000 {
compatible = "qcom,qcedev";
reg = <0x720000 0x20000>,
<0x704000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,msm-bus,name = "qcedev-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<47 512 0 0>,
<47 512 393600 393600>;
/*TODO: Fix the clock when tree is available*/
clock-names = "core_clk", "iface_clk",
"bus_clk","core_clk_src";
qcom,ce-opp-freq = <171430000>;
};
qcom,qcrypto@720000 {
compatible = "qcom,qcrypto";
reg = <0x720000 0x20000>,
<0x704000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,msm-bus,name = "qcrypto-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<47 512 0 0>,
<47 512 393600 393600>;
/*TODO: Fix the clock when tree is available*/
clock-names = "core_clk", "iface_clk",
"bus_clk","core_clk_src";
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
qcom,use-sw-hmac-algo;
qcom,use-sw-aead-algo;
qcom,ce-opp-freq = <171430000>;
};
qcom_seecom: qseecom@87800000 {
compatible = "qcom,qseecom";
reg = <0x87800000 0x200000>;
reg-names = "secapp-region";
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,msm-bus,name = "qseecom-noc";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<47 512 0 0>,
<47 512 200000 400000>,
<47 512 300000 800000>,
<47 512 400000 1000000>;
/*TODO: Fix the clock when tree is available*/
clock-names = "core_clk", "iface_clk",
"bus_clk","core_clk_src";
qcom,ce-opp-freq = <100000000>;
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <0 108 0>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b1000 0x200>;
interrupts = <0 109 0>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
qcom,wdt@b017000 {
compatible = "qcom,msm-watchdog";
reg = <0xb017000 0x1000>;
reg-names = "wdt-base";
interrupts = <1 3 0>, <1 2 0>;
qcom,bark-time = <11000>;
qcom,pet-time = <10000>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
jtag_mm0: jtagmm@842000 {
compatible = "qcom,jtag-mm";
reg = <0x842000 0x1000>,
<0x840000 0x1000>;
reg-names = "etm-base","debug-base";
qcom,coresight-jtagmm-cpu = <&CPU0>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
};
tcsr_mutex_regs: syscon@1905000 {
compatible = "syscon";
reg = <0x1905000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
apcs_glb: mailbox@0xb011008 {
compatible = "qcom,sdxnightjar-apcs-gcc";
reg = <0xb011008 0x4>;
#mbox-cells = <1>;
};
rpm_msg_ram: memory@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x60000 0x6000>;
};
smem_mem: smem_region@87e80000 {
reg = <0x87e80000 0xc0000>;
no-map;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&tcsr_mutex 3>;
};
qcom,smd {
compatible = "qcom,smd";
modem {
qcom,smd-edge = <0>;
mboxes = <&apcs_glb 12>;
qcom,remote-pid = <1>;
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
label = "mpss";
qcom,smd-channels = "IPCRTR";
qcom,modem_qrtr {
qcom,low-latency;
};
};
rpm {
qcom,smd-edge = <15>;
mboxes = <&apcs_glb 0>;
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
label = "rpm";
rpm_requests: rpm_requests@0 {
compatible = "qcom,rpm-smd";
qcom,smd-channels = "rpm_requests";
};
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&apcs_glb 15>;
mbox-names = "mpss_smem";
interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-data5-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA5_CNTL";
qcom,glinkpkt-dev-name = "smdcntl0";
};
qcom,glinkpkt-data6-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA6_CNTL";
qcom,glinkpkt-dev-name = "smdcntl1";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
qcom,glinkpkt-data21 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA21";
qcom,glinkpkt-dev-name = "smd21";
};
qcom,glinkpkt-data22 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA22";
qcom,glinkpkt-dev-name = "smd22";
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qnand_1: nand@7980000 {
compatible = "qcom,msm-nand";
reg = <0x07980000 0x1000>,
<0x07984000 0x1a000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>;
interconnect-names = "nand-ddr";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<0 0>,
/* Voting for max b/w on PNOC bus for now */
<400000 400000>;
status = "disabled";
};
sdhc_1: sdhci@7824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07824900 0x500>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,devfreq,freq-table = <50000000 200000000>;
interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
interconnect-names = "sdhc-ddr";
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */
<1600 3200>, /* 400 KB/s*/
<100000 200000>, /* 25 MB/s */
<200000 400000>, /* 50 MB/s */
<400000 800000>, /* 100 MB/s */
<400000 800000>, /* 200 MB/s */
<2048000 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 4294967295>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
status = "disabled";
qos0 {
mask = <0x1>;
vote = <70>;
};
};
spmi_bus: qcom,spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000>,
<0x2400000 0x800000>,
<0x2c00000 0x800000>,
<0x3800000 0x200000>,
<0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts = <0 190 0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,pmic-arb-max-peripherals = <256>;
qcom,pmic-arb-max-periph-interrupts = <256>;
#interrupt-cells = <4>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
};
bimc: interconnect@400000 {
reg = <0x400000 0x62000>;
compatible = "qcom,sdxnightjar-bimc";
qcom,util-factor = <153>;
qcom,keepalive;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
pc_noc: interconnect@500000 {
reg = <0x500000 0x11000>;
compatible = "qcom,sdxnightjar-pcnoc";
qcom,keepalive;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
system_noc: interconnect@580000 {
reg = <0x580000 0x14000>;
compatible = "qcom,sdxnightjar-snoc";
qcom,keepalive;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
};
ipa_hw: qcom,ipa@07B00000 {
compatible = "qcom,ipa";
reg = <0x07B00000 0x34000>,
<0x07B84000 0x31FFFF>,
<0x07B04000 0x2C000>;
reg-names = "ipa-base", "bam-base", "gsi-base";
interrupts =
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
qcom,ipa-hw-ver = <10>; /* IPA core version = IPAv3.0 */
qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
qcom,platform-type = <0>; /* MDM platform */
qcom,ee = <0>;
qcom,use-rg10-limitation-mitigation;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
clock-names = "core_clk";
clocks = <&rpmcc RPM_SMD_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>,
<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
<&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<80000 64000 80000 64000 80000 16000>;
/* SVS */
qcom,svs =
<80000 640000 80000 640000 80000 160000>;
/* NOMINAL */
qcom,nominal =
<206000 960000 206000 960000 206000 400000>;
/* TURBO */
qcom,turbo =
<206000 3600000 206000 3600000 206000 960000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
qcom,throughput-threshold = <310 600 1000>;
qcom,scaling-exceptions = <>;
/* ipa tz unlock registers */
qcom,ipa-tz-unlock-reg =
<0x4043583c 0x1000>; /* 32-bit reg addr and size */
/* smp2p gpio information */
qcom,smp2pgpio_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2pgpio_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
};
};
#include "pmd9650.dtsi"
#include "pmd9650-rpm-regulator.dtsi"
#include "sdxnightjar-regulator.dtsi"
#include "sdxnightjar-usb.dtsi"
#include "sdxnightjar-coresight.dtsi"
#include "sdxnightjar-pinctrl.dtsi"
#include "sdxnightjar-blsp.dtsi"
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