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ASoC: cs35l41: Rev B0 register defaults

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* Fix register defaults that changed with chip revision B0.

* regmap_register_patch() has a bug which will cause register writes
to be delivered to the chip, but NOT the regcache. This can cause the
regcache to become out of sync with the actual state of the registers.
Changed the usage of this function to regmap_multi_reg_write() to
avoid this problem.

SQA-860

Mot-CRs-fixed: (CR): River: AoU bringup on Marley+Prince
Change-Id: I512cffd656fdf942b7fcafc2a0473a7449cf2547
Signed-off-by: Adam Brickman <Adam.Brickman@cirrus.com>
Reviewed-on: https://gerrit.mot.com/1238848
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
SLTApproved: Slta Waiver
Reviewed-by: Konstantin Makariev <kmakariev@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
Adam Brickman 2018-07-06 15:35:17 -05:00 • committed by Patrick Gries
commit cd72ed7a2a
2 changed files with 6 additions and 1 deletions
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6
sound/soc/codecs/cs35l41.c
View file

@ -1870,7 +1870,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
switch (reg_revid) {
case CS35L41_REVID_A0:
ret = regmap_register_patch(cs35l41->regmap,
ret = regmap_multi_reg_write(cs35l41->regmap,
cs35l41_reva0_errata_patch,
ARRAY_SIZE(cs35l41_reva0_errata_patch));
if (ret < 0) {
@ -1878,6 +1878,10 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
"Failed to apply A0 errata patch %d\n", ret);
goto err;
}
break;
case CS35L41_REVID_B0:
regmap_write(cs35l41->regmap, CS35L41_BSTCVRT_DCM_CTRL, 0x51);
break;
}
ret = cs35l41_otp_unpack(cs35l41);

1
sound/soc/codecs/cs35l41.h
View file

@ -696,6 +696,7 @@
#define CS35L41R_CHIP_ID 0x35b40
#define CS35L41_MTLREVID_MASK 0x0F
#define CS35L41_REVID_A0 0xA0
#define CS35L41_REVID_B0 0xB0
#define CS35L41_DSP_N_RX_RATES 8
#define CS35L41_DSP_N_TX_RATES 8