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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add GPU support for monaco IoT
Add devicetree node for A702 GPU and its properties. Change-Id: If1d446493e5dc6a1bcda553e023427ba7593d3d6
This commit is contained in:
Amit Kushwaha
Gerrit - the friendly Code Review server
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2 changed files with 197 additions and 0 deletions
196
qcom/monaco-gpu.dtsi
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196
qcom/monaco-gpu.dtsi
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a702_zap";
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memory-region = <&pil_gpu_mem>;
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};
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msm_gpu: qcom,kgsl-3d0@5900000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0";
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status = "ok"
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reg = <0x5900000 0x90000>,
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<0x5961000 0x800>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
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interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,chipid = <0x07000201>;
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qcom,initial-pwrlevel = <4>;
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qcom,idle-timeout = <80>;
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qcom,gpu-bimc-interface-clk-freq = <768000000>;
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qcom,ubwc-mode = <2>;
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qcom,min-access-length = <64>;
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/* base addr, size */
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qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
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#cooling-cells = <2>;
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_BIMC_GPU_AXI_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&rpmcc RPM_SMD_BIMC_GPU_CLK>;
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clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
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"iface_clk", "mem_iface_clk", "gmu_clk",
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"smmu_vote", "bimc_gpu_clk";
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* Context aware jump target power level */
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qcom,ca-target-pwrlevel = <3>;
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interconnect-names = "gpu_icc_path";
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interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
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qcom,bus-table-ddr7 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 */
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<MHZ_TO_KBPS(300, 4)>, /* index=2 */
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<MHZ_TO_KBPS(451, 4)>, /* index=3 */
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<MHZ_TO_KBPS(547, 4)>, /* index=4 */
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<MHZ_TO_KBPS(681, 4)>, /* index=5 */
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<MHZ_TO_KBPS(768, 4)>, /* index=6 */
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<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
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<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
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<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=11 */
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<MHZ_TO_KBPS(2133, 4)>; /* index=12 */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1010000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <12>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <12>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <11>;
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qcom,bus-min-ddr7 = <11>;
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qcom,bus-max-ddr7 = <12>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <700000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <470000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <310000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <3>;
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qcom,bus-max-ddr7 = <4>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x59a0000 0x10000>;
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vddcx-supply = <&gpu_cx_gdsc>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0 1>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 2 0>;
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qcom,iommu-dma = "disabled";
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};
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};
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};
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@ -1377,6 +1377,7 @@
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#include "monaco-usb.dtsi"
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#include "monaco-thermal.dtsi"
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#include "monaco-vidc.dtsi"
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#include "monaco-gpu.dtsi"
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&qupv3_se6_2uart {
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status = "ok"
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