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ARM: dts: msm: enable SDE RSC rev 4 on lahaina

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Enable the SDE RSC rev4 driver and HW, and update the
interconnect bindings.

Change-Id: I85336dac6d0c4081350259c636c1159c32c582a5
This commit is contained in:
Steven Cohen 2020-03-14 19:38:40 -04:00 • committed by Steve Cohen
commit d7ae7e47af
2 changed files with 14 additions and 23 deletions
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2
display/lahaina-sde-display.dtsi
View file

@ -141,7 +141,7 @@
};
&mdss_mdp {
connectors = <&sde_dp &sde_wb &sde_dsi>;
connectors = <&sde_dp &sde_wb &sde_dsi &sde_rscc>;
};
/* PHY TIMINGS REVISION YB */

35
display/lahaina-sde.dtsi
View file

@ -29,7 +29,6 @@
460000000>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
vdd-supply = <&disp_cc_mdss_core_gdsc>;
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@ -235,14 +234,12 @@
qcom,sde-secure-sid-mask = <0x4000821>;
/* data and reg bus scale settings */
interconnects =
<&mmss_noc MASTER_MDP0 &gem_noc SLAVE_LLCC>,
<&mmss_noc MASTER_MDP1 &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
"qcom,sde-reg-bus";
qcom,sde-sspp-vig-blocks {
qcom,sde-vig-csc-off = <0x1a00>;
@ -294,15 +291,6 @@
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
qcom,platform-supply-entry@1 {
reg = <0>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
@ -461,11 +449,10 @@
sde_rscc: qcom,sde_rscc@af20000 {
cell-index = <0>;
compatible = "qcom,sde-rsc";
status = "disabled";
reg = <0xaf20000 0x3c50>,
reg = <0xaf20000 0x4d68>,
<0xaf30000 0x3fd4>;
reg-names = "drv", "wrapper";
qcom,sde-rsc-version = <3>;
qcom,sde-rsc-version = <4>;
qcom,sde-dram-channels = <2>;
@ -474,10 +461,14 @@
<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
qcom,msm-bus,active-only;
interconnects =
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-reg-bus";
<&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>,
<&mmss_noc MASTER_MDP1_DISP &gem_noc SLAVE_LLCC_DISP>,
<&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
"qcom,sde-ebi-bus";
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {