ARM: dts: msm: fix for Shima-CAMNOC RDI latency buffer corruption

This is a fix to handle line corruption on RDI stream by capping
IPE clock to SVS. It will help to avoid back pressure on CAMNOC
dur to IPE traffic. This gives more room to IFE RDI stream and hence
avoid corruption.

CRs-Fixed: 2887253
Change-Id: I8880c08d507ebb90b447815a241870d03fd24bec
This commit is contained in:
Alok Pandey 2021-01-27 22:31:37 +05:30 • committed by Gerrit - the friendly Code Review server
commit db2bf32358

View file

@ -1215,9 +1215,9 @@
clock-rates =
<0 0 0 300000000 0>,
<0 0 0 450000000 0>,
<0 0 0 525000000 0>,
<0 0 0 700000000 0>,
<0 0 0 700000000 0>;
<0 0 0 450000000 0>,
<0 0 0 450000000 0>,
<0 0 0 450000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
status = "ok"