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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: add DCVS nodes for shima target
Add DCVS nodes to scale L3, LLCC and DDR based on the traffic for shima target. Change-Id: I129119f4ffb4b1c897ef2281eacab8ef21be05d2
This commit is contained in:
Santosh Mardi
Gerrit - the friendly Code Review server
parent
52f57a24c4
commit
e3c839b105
1 changed files with 523 additions and 0 deletions
523
qcom/shima.dtsi
523
qcom/shima.dtsi
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@ -15,6 +15,14 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
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opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
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opp-supported-hw = <ddrtype>;}
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#define DDR_TYPE_LPDDR4X 7
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#define DDR_TYPE_LPDDR5 8
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/ {
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model = "Qualcomm Technologies, Inc. Shima";
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compatible = "qcom,shima";
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@ -1737,6 +1745,521 @@
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status = "disabled";
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};
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llcc_pmu: llcc-pmu@9095000 {
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compatible = "qcom,llcc-pmu-ver2";
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reg = <0x09095000 0x300>;
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reg-names = "lagg-base";
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};
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llcc_bw_opp_table: llcc-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */
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BW_OPP_ENTRY( 300, 32); /* 9154 MB/s */
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BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */
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BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */
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BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */
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BW_OPP_ENTRY( 933, 32); /* 28472 MB/s */
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BW_OPP_ENTRY( 1066, 32); /* 30516 MB/s */
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};
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ddr_bw_opp_table: ddr-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
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BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
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BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
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BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
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BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
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BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
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BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /* 6515 MB/s */
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BW_OPP_ENTRY_DDR( 2092, 4, 0x100); /* 7980 MB/s */
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BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */
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BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
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BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */
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};
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qoslat_opp_table: qoslat-opp-table {
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compatible = "operating-points-v2";
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opp-1 {
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opp-hz = /bits/ 64 < 1 >;
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};
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opp-2 {
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opp-hz = /bits/ 64 < 2 >;
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};
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};
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cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
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compatible = "qcom,devfreq-icc";
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governor = "bw_hwmon";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
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compatible = "qcom,bimc-bwmon4";
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reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
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reg-names = "base", "global_base";
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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qcom,mport = <0>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_cpu_llcc_bw>;
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qcom,count-unit = <0x10000>;
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};
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cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "bw_hwmon";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
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compatible = "qcom,bimc-bwmon5";
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reg = <0x9091000 0x1000>;
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reg-names = "base";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_llcc_ddr_bw>;
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qcom,count-unit = <0x10000>;
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};
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cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
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};
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cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
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};
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cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
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};
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cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
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};
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cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
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};
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cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
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};
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cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
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};
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cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "mem_latency";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
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};
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cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "mem_latency";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "mem_latency";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "mem_latency";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "mem_latency";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "compute";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "compute";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {
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compatible = "qcom,devfreq-icc";
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governor = "compute";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "compute";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
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compatible = "qcom,devfreq-qoslat";
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governor = "mem_latency";
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operating-points-v2 = <&qoslat_opp_table>;
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mboxes = <&qmp_aop 0>;
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};
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cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
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qcom,core-dev-table =
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< 300000 300000000 >,
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< 691200 556800000 >,
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< 940800 652800000 >,
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< 1171200 844800000 >,
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< 1516800 1065600000 >,
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< 1670400 1305600000 >,
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< 1804800 1420800000 >;
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};
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cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {
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qcom,core-dev-table =
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< 940800 556800000 >,
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< 1209600 806400000 >,
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< 1651200 1190400000 >,
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< 1900800 1401600000 >,
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< 2361600 1420800000 >;
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};
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cpu7_cpu_l3_tbl: qcom,cpu7-cpu-l3-tbl {
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qcom,core-dev-table =
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< 1094400 556800000 >,
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< 1267200 806400000 >,
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< 1766400 1190400000 >,
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< 2227200 1401600000 >,
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< 2707200 1420800000 >;
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};
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cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
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compatible = "qcom,arm-memlat-cpugrp";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
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cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0>;
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qcom,target-dev = <&cpu0_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
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};
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cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU1>;
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qcom,target-dev = <&cpu1_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
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};
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cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU2>;
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qcom,target-dev = <&cpu2_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
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};
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cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU3>;
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qcom,target-dev = <&cpu3_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
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};
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cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU4>;
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qcom,target-dev = <&cpu4_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,access-ev = <0x2B>;
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qcom,wb-ev = <0x18>;
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qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
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};
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cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU5>;
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qcom,target-dev = <&cpu5_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,access-ev = <0x2B>;
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qcom,wb-ev = <0x18>;
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qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
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};
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cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU6>;
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qcom,target-dev = <&cpu6_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,access-ev = <0x2B>;
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qcom,wb-ev = <0x18>;
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qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
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};
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cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU7>;
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qcom,target-dev = <&cpu7_cpu_l3_lat>;
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qcom,cachemiss-ev = <0x17>;
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qcom,access-ev = <0x2B>;
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qcom,wb-ev = <0x18>;
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qcom,core-dev-table = <&cpu7_cpu_l3_tbl>;
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};
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cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,target-dev = <&cpu0_cpu_llcc_lat>;
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
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qcom,cachemiss-ev = <0x2A>;
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qcom,core-dev-table =
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< 1171200 MHZ_TO_MBPS( 300, 32) >,
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< 1516800 MHZ_TO_MBPS( 466, 32) >,
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< 1804800 MHZ_TO_MBPS( 600, 32) >;
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};
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cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
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qcom,target-dev = <&cpu0_llcc_ddr_lat>;
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qcom,cachemiss-ev = <0x1000>;
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ddr4-map {
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qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 940800 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1171200 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1516800 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1804800 MHZ_TO_MBPS( 1017, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 691200 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 940800 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1171200 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1516800 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1804800 MHZ_TO_MBPS( 1555, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_computemon: qcom,cpu0-computemon {
|
||||
compatible = "qcom,arm-compute-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
||||
qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 200, 4) >,
|
||||
< 1171200 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1516800 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1804800 MHZ_TO_MBPS( 768, 4) >;
|
||||
};
|
||||
|
||||
cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_llcc_lat>;
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
qcom,cachemiss-ev = <0x2A>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 300, 32) >,
|
||||
< 940800 MHZ_TO_MBPS( 466, 32) >,
|
||||
< 1209600 MHZ_TO_MBPS( 600, 32) >,
|
||||
< 1651800 MHZ_TO_MBPS( 806, 32) >,
|
||||
< 2361600 MHZ_TO_MBPS( 933, 32) >,
|
||||
< 2707200 MHZ_TO_MBPS( 1066, 32) >;
|
||||
};
|
||||
|
||||
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
|
||||
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
ddr4-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 940800 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1209600 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 1651800 MHZ_TO_MBPS(1555, 4) >,
|
||||
< 2361600 MHZ_TO_MBPS(1708, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(2133, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 940800 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1209600 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 1651800 MHZ_TO_MBPS(1555, 4) >,
|
||||
< 1900800 MHZ_TO_MBPS(1708, 4) >,
|
||||
< 2361600 MHZ_TO_MBPS(2092, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(3196, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU7>;
|
||||
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
ddr4-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
|
||||
qcom,core-dev-table =
|
||||
< 2361600 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(2133, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 2361600 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(3196, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4_computemon: qcom,cpu4-computemon {
|
||||
compatible = "qcom,arm-compute-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
|
||||
ddr4-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1209600 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1497600 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1651800 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 1900800 MHZ_TO_MBPS(1555, 4) >,
|
||||
< 2361600 MHZ_TO_MBPS(1708, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(2133, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 691000 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1209600 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1497600 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1651800 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 1900800 MHZ_TO_MBPS(1708, 4) >,
|
||||
< 2361600 MHZ_TO_MBPS(2092, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(3196, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {
|
||||
compatible = "qcom,arm-compute-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
qcom,core-dev-table =
|
||||
< 1900800 MHZ_TO_MBPS( 150, 32) >,
|
||||
< 2707200 MHZ_TO_MBPS( 600, 32) >;
|
||||
};
|
||||
|
||||
cpu7_computemon: qcom,cpu7-computemon {
|
||||
compatible = "qcom,arm-compute-mon";
|
||||
qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;
|
||||
qcom,cpulist = <&CPU7>;
|
||||
ddr4-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
|
||||
qcom,core-dev-table =
|
||||
< 2361600 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(2033, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 2361600 MHZ_TO_MBPS( 300, 4) >,
|
||||
< 2707200 MHZ_TO_MBPS(3196, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4_qoslatmon: qcom,cpu4-qoslatmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 1 >,
|
||||
< 3000000 2 >;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sps {
|
||||
compatible = "qcom,msm-sps-4k";
|
||||
qcom,pipe-attr-ee;
|
||||
|
|
|
|||
Loading…
Reference in a new issue