A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Change data size for PCIe write halt

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Update value from 1MB to 256B for PCI RC 1 (3x2).
This is a software workaround to prevent system
bus deadlock issue with concurrent access of
greater than 256B granularity from two PCIe
ports to DDR.

Change-Id: I9461e97a70f58b7ca3070881f208615a0624f5b6
This commit is contained in:
Hemant Kumar 2020-08-03 19:35:38 -07:00
commit e4782dcbf3
1 changed files with 1 additions and 0 deletions
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1
qcom/lahaina-pcie.dtsi
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@ -330,6 +330,7 @@
qcom,boot-option = <0x1>;
qcom,drv-supported;
qcom,use-19p2mhz-aux-clk;
qcom,wr-halt-size = <0x8>;
qcom,no-l0s-supported;
qcom,slv-addr-space-size = <0x20000000>;
qcom,ep-latency = <10>;