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clk: qcom: gdsc-regulator: Remove polling logic when disabling GDSC HW CTL

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There is no mandate in hardware that the SW_COLLAPSE bit of the
GDSC be cleared while disabling its hardware control. Remove the
polling logic to check whether the GDSC is enabled via the SW
vote on clearing the HW_CONTROL bit.

Change-Id: Ib08b627a3502d1096ae7d05ef077a50b95fc80d2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2018-05-16 11:00:29 -07:00 • committed by David Collins
commit eade63525a
1 changed files with 2 additions and 8 deletions
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10
drivers/clk/qcom/gdsc-regulator.c
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@ -500,17 +500,11 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode)
/*
* There may be a race with internal HW trigger signal,
* that will result in GDSC going through a power down and
* up cycle. If we poll too early, status bit will
* indicate 'on' before the GDSC can finish the power cycle.
* Account for this case by waiting 1us before polling.
* up cycle. Account for this case by waiting 1us before
* proceeding.
*/
gdsc_mb(sc);
udelay(1);
ret = poll_gdsc_status(sc, ENABLED);
if (ret)
dev_err(&rdev->dev, "%s set_mode timed out: 0x%x\n",
sc->rdesc.name, regval);
break;
default:
ret = -EINVAL;