mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 20:33:58 -04:00
cpufreq: qcom: Add snapshot of cpufreq-hw
This is snapshot of the cpufreq-hw as of msm-4.19
'commit b75185bdb985 ("cpufreq: qcom-hw:
Add support for QCOM cpufreq HW driver")'.
Change-Id: Ibd5bcf763513ba959e67eb736e707f30d30a41b0
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
parent
7db9be171f
commit
ed7c3ccb4a
1 changed files with 202 additions and 194 deletions
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@ -1,52 +1,59 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_L_VAL GENMASK(7, 0)
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#define LUT_CORE_COUNT GENMASK(18, 16)
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#define LUT_VOLT GENMASK(11, 0)
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#define CORE_COUNT_VAL(val) (((val) & (GENMASK(18, 16))) >> 16)
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#define LUT_ROW_SIZE 32
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#define CLK_HW_DIV 2
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#define LUT_TURBO_IND 1
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/* Register offsets */
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#define REG_ENABLE 0x0
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#define REG_FREQ_LUT 0x110
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#define REG_VOLT_LUT 0x114
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#define REG_PERF_STATE 0x920
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enum {
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REG_ENABLE,
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REG_LUT_TABLE,
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REG_PERF_STATE,
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static unsigned long cpu_hw_rate, xo_rate;
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static struct platform_device *global_pdev;
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REG_ARRAY_SIZE,
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};
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static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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struct cpufreq_qcom {
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struct cpufreq_frequency_table *table;
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void __iomem *reg_bases[REG_ARRAY_SIZE];
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cpumask_t related_cpus;
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unsigned int max_cores;
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unsigned long xo_rate;
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unsigned long cpu_hw_rate;
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};
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static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = {
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[REG_ENABLE] = 0x0,
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[REG_LUT_TABLE] = 0x110,
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[REG_PERF_STATE] = 0x920,
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};
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static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS];
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static int
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qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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{
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void __iomem *perf_state_reg = policy->driver_data;
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unsigned long freq = policy->freq_table[index].frequency;
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struct cpufreq_qcom *c = policy->driver_data;
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writel_relaxed(index, perf_state_reg);
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writel_relaxed(index, c->reg_bases[REG_PERF_STATE]);
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arch_set_freq_scale(policy->related_cpus, freq,
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policy->cpuinfo.max_freq);
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return 0;
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}
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static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
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{
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void __iomem *perf_state_reg;
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struct cpufreq_qcom *c;
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struct cpufreq_policy *policy;
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unsigned int index;
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@ -54,208 +61,45 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
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if (!policy)
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return 0;
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perf_state_reg = policy->driver_data;
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c = policy->driver_data;
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index = readl_relaxed(perf_state_reg);
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index = readl_relaxed(c->reg_bases[REG_PERF_STATE]);
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index = min(index, LUT_MAX_ENTRIES - 1);
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return policy->freq_table[index].frequency;
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}
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static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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static unsigned int
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qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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void __iomem *perf_state_reg = policy->driver_data;
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struct cpufreq_qcom *c = policy->driver_data;
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int index;
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unsigned long freq;
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index = policy->cached_resolved_idx;
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if (index < 0)
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return 0;
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writel_relaxed(index, perf_state_reg);
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writel_relaxed(index, c->reg_bases[REG_PERF_STATE]);
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freq = policy->freq_table[index].frequency;
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arch_set_freq_scale(policy->related_cpus, freq,
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policy->cpuinfo.max_freq);
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return freq;
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}
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static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
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struct cpufreq_policy *policy,
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void __iomem *base)
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{
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u32 data, src, lval, i, core_count, prev_freq = 0, freq;
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u32 volt;
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struct cpufreq_frequency_table *table;
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table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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data = readl_relaxed(base + REG_FREQ_LUT +
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i * LUT_ROW_SIZE);
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src = FIELD_GET(LUT_SRC, data);
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lval = FIELD_GET(LUT_L_VAL, data);
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core_count = FIELD_GET(LUT_CORE_COUNT, data);
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data = readl_relaxed(base + REG_VOLT_LUT +
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i * LUT_ROW_SIZE);
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volt = FIELD_GET(LUT_VOLT, data) * 1000;
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if (src)
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freq = xo_rate * lval / 1000;
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else
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freq = cpu_hw_rate / 1000;
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if (freq != prev_freq && core_count != LUT_TURBO_IND) {
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table[i].frequency = freq;
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dev_pm_opp_add(cpu_dev, freq * 1000, volt);
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dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
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freq, core_count);
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} else if (core_count == LUT_TURBO_IND) {
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table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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/*
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* Two of the same frequencies with the same core counts means
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* end of table
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*/
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if (i > 0 && prev_freq == freq) {
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struct cpufreq_frequency_table *prev = &table[i - 1];
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/*
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* Only treat the last frequency that might be a boost
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* as the boost frequency
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*/
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if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
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prev->frequency = prev_freq;
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prev->flags = CPUFREQ_BOOST_FREQ;
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dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt);
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}
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break;
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}
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prev_freq = freq;
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}
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table[i].frequency = CPUFREQ_TABLE_END;
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policy->freq_table = table;
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dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
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return 0;
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}
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static void qcom_get_related_cpus(int index, struct cpumask *m)
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{
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struct device_node *cpu_np;
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struct of_phandle_args args;
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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cpu_np = of_cpu_device_node_get(cpu);
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if (!cpu_np)
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continue;
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0,
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&args);
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of_node_put(cpu_np);
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if (ret < 0)
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continue;
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if (index == args.args[0])
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cpumask_set_cpu(cpu, m);
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}
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return policy->freq_table[index].frequency;
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}
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static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
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{
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struct device *dev = &global_pdev->dev;
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struct of_phandle_args args;
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struct device_node *cpu_np;
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struct device *cpu_dev;
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struct resource *res;
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void __iomem *base;
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int ret, index;
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struct cpufreq_qcom *c;
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cpu_dev = get_cpu_device(policy->cpu);
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if (!cpu_dev) {
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pr_err("%s: failed to get cpu%d device\n", __func__,
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policy->cpu);
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c = qcom_freq_domain_map[policy->cpu];
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if (!c) {
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pr_err("No scaling support for CPU%d\n", policy->cpu);
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return -ENODEV;
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}
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cpu_np = of_cpu_device_node_get(policy->cpu);
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if (!cpu_np)
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return -EINVAL;
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0, &args);
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of_node_put(cpu_np);
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if (ret)
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return ret;
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index = args.args[0];
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res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);
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if (!res)
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return -ENODEV;
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base = devm_ioremap(dev, res->start, resource_size(res));
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if (!base)
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return -ENOMEM;
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/* HW should be in enabled state to proceed */
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if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
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dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
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ret = -ENODEV;
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goto error;
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}
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qcom_get_related_cpus(index, policy->cpus);
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if (!cpumask_weight(policy->cpus)) {
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dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
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ret = -ENOENT;
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goto error;
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}
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policy->driver_data = base + REG_PERF_STATE;
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ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
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if (ret) {
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dev_err(dev, "Domain-%d failed to read LUT\n", index);
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goto error;
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}
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ret = dev_pm_opp_get_opp_count(cpu_dev);
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if (ret <= 0) {
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dev_err(cpu_dev, "Failed to add OPPs\n");
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ret = -ENODEV;
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goto error;
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}
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dev_pm_opp_of_register_em(policy->cpus);
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cpumask_copy(policy->cpus, &c->related_cpus);
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policy->fast_switch_possible = true;
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return 0;
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error:
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devm_iounmap(dev, base);
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return ret;
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}
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static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
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{
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struct device *cpu_dev = get_cpu_device(policy->cpu);
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void __iomem *base = policy->driver_data - REG_PERF_STATE;
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dev_pm_opp_remove_all_dynamic(cpu_dev);
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kfree(policy->freq_table);
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devm_iounmap(&global_pdev->dev, base);
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policy->freq_table = c->table;
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policy->driver_data = c;
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return 0;
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}
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@ -268,62 +112,233 @@ static struct freq_attr *qcom_cpufreq_hw_attr[] = {
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static struct cpufreq_driver cpufreq_qcom_hw_driver = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_IS_COOLING_DEV,
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CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = qcom_cpufreq_hw_target_index,
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.get = qcom_cpufreq_hw_get,
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.init = qcom_cpufreq_hw_cpu_init,
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.exit = qcom_cpufreq_hw_cpu_exit,
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.fast_switch = qcom_cpufreq_hw_fast_switch,
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.name = "qcom-cpufreq-hw",
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.attr = qcom_cpufreq_hw_attr,
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.boost_enabled = true,
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};
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static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev,
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struct cpufreq_qcom *c)
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{
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struct device *dev = &pdev->dev;
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void __iomem *base;
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u32 data, src, lval, i, core_count, prev_cc, prev_freq, cur_freq;
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c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,
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sizeof(*c->table), GFP_KERNEL);
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if (!c->table)
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return -ENOMEM;
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base = c->reg_bases[REG_LUT_TABLE];
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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data = readl_relaxed(base + i * LUT_ROW_SIZE);
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src = (data & GENMASK(31, 30)) >> 30;
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lval = data & GENMASK(7, 0);
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core_count = CORE_COUNT_VAL(data);
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if (src)
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c->table[i].frequency = c->xo_rate * lval / 1000;
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else
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c->table[i].frequency = c->cpu_hw_rate / 1000;
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cur_freq = c->table[i].frequency;
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dev_dbg(dev, "index=%d freq=%d, core_count %d\n",
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i, c->table[i].frequency, core_count);
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if (core_count != c->max_cores)
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cur_freq = CPUFREQ_ENTRY_INVALID;
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/*
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* Two of the same frequencies with the same core counts means
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* end of table.
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*/
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if (i > 0 && c->table[i - 1].frequency ==
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c->table[i].frequency && prev_cc == core_count) {
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struct cpufreq_frequency_table *prev = &c->table[i - 1];
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if (prev_freq == CPUFREQ_ENTRY_INVALID)
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prev->flags = CPUFREQ_BOOST_FREQ;
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break;
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}
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prev_cc = core_count;
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prev_freq = cur_freq;
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}
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c->table[i].frequency = CPUFREQ_TABLE_END;
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return 0;
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}
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static int qcom_get_related_cpus(int index, struct cpumask *m)
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{
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struct device_node *cpu_np;
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struct of_phandle_args args;
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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cpu_np = of_cpu_device_node_get(cpu);
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if (!cpu_np)
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continue;
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of_node_put(cpu_np);
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0, &args);
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if (ret < 0)
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continue;
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if (index == args.args[0])
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cpumask_set_cpu(cpu, m);
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}
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return 0;
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}
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static int qcom_cpu_resources_init(struct platform_device *pdev,
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unsigned int cpu, int index,
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unsigned long xo_rate,
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unsigned long cpu_hw_rate)
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{
|
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struct cpufreq_qcom *c;
|
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struct resource *res;
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struct device *dev = &pdev->dev;
|
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const u16 *offsets;
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int ret, i, cpu_r;
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void __iomem *base;
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if (qcom_freq_domain_map[cpu])
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return 0;
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c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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return -ENOMEM;
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offsets = of_device_get_match_data(&pdev->dev);
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if (!offsets)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, index);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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for (i = REG_ENABLE; i < REG_ARRAY_SIZE; i++)
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c->reg_bases[i] = base + offsets[i];
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/* HW should be in enabled state to proceed */
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if (!(readl_relaxed(c->reg_bases[REG_ENABLE]) & 0x1)) {
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dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
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return -ENODEV;
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}
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ret = qcom_get_related_cpus(index, &c->related_cpus);
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if (ret) {
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dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
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return ret;
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}
|
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c->max_cores = cpumask_weight(&c->related_cpus);
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if (!c->max_cores)
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return -ENOENT;
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c->xo_rate = xo_rate;
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c->cpu_hw_rate = cpu_hw_rate;
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ret = qcom_cpufreq_hw_read_lut(pdev, c);
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if (ret) {
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dev_err(dev, "Domain-%d failed to read LUT\n", index);
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return ret;
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}
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|
||||
for_each_cpu(cpu_r, &c->related_cpus)
|
||||
qcom_freq_domain_map[cpu_r] = c;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_resources_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *cpu_np;
|
||||
struct of_phandle_args args;
|
||||
struct clk *clk;
|
||||
unsigned int cpu;
|
||||
unsigned long xo_rate, cpu_hw_rate;
|
||||
int ret;
|
||||
|
||||
clk = clk_get(&pdev->dev, "xo");
|
||||
clk = devm_clk_get(&pdev->dev, "xo");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
xo_rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
clk = clk_get(&pdev->dev, "alternate");
|
||||
devm_clk_put(&pdev->dev, clk);
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "cpu_clk");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
|
||||
clk_put(clk);
|
||||
|
||||
global_pdev = pdev;
|
||||
devm_clk_put(&pdev->dev, clk);
|
||||
|
||||
ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
|
||||
else
|
||||
dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
|
||||
for_each_possible_cpu(cpu) {
|
||||
cpu_np = of_cpu_device_node_get(cpu);
|
||||
if (!cpu_np) {
|
||||
dev_dbg(&pdev->dev, "Failed to get cpu %d device\n",
|
||||
cpu);
|
||||
continue;
|
||||
}
|
||||
|
||||
return ret;
|
||||
ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
|
||||
"#freq-domain-cells", 0, &args);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = qcom_cpu_resources_init(pdev, cpu, args.args[0],
|
||||
xo_rate, cpu_hw_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
|
||||
static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
|
||||
{
|
||||
return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
|
||||
int rc;
|
||||
|
||||
/* Get the bases of cpufreq for domains */
|
||||
rc = qcom_resources_init(pdev);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "CPUFreq resource init failed\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_cpufreq_hw_match[] = {
|
||||
{ .compatible = "qcom,cpufreq-hw" },
|
||||
{ .compatible = "qcom,cpufreq-hw", .data = &cpufreq_qcom_std_offsets },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
|
||||
|
||||
static struct platform_driver qcom_cpufreq_hw_driver = {
|
||||
.probe = qcom_cpufreq_hw_driver_probe,
|
||||
.remove = qcom_cpufreq_hw_driver_remove,
|
||||
.driver = {
|
||||
.name = "qcom-cpufreq-hw",
|
||||
.of_match_table = qcom_cpufreq_hw_match,
|
||||
|
|
@ -334,13 +349,6 @@ static int __init qcom_cpufreq_hw_init(void)
|
|||
{
|
||||
return platform_driver_register(&qcom_cpufreq_hw_driver);
|
||||
}
|
||||
device_initcall(qcom_cpufreq_hw_init);
|
||||
subsys_initcall(qcom_cpufreq_hw_init);
|
||||
|
||||
static void __exit qcom_cpufreq_hw_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&qcom_cpufreq_hw_driver);
|
||||
}
|
||||
module_exit(qcom_cpufreq_hw_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("QCOM firmware-based CPU Frequency driver");
|
||||
|
|
|
|||
Loading…
Reference in a new issue