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disp: msm: dsi: add support to set continuous clock through phy

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For phy ver 4.0 chipsets, configure DSI controller and DSI PHY to
force clk lane to HS mode always. This change was missed while
propagating from 4.19 to 5.4.

Change-Id: I60370034f7b9ed5d036d9d22f0807250afbcbcd5
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
This commit is contained in:
Ritesh Kumar 2019-11-01 12:37:55 +05:30
commit ee90425ea7
1 changed files with 13 additions and 1 deletions
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14
msm/dsi/dsi_display.c
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@ -1069,7 +1069,19 @@ static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
display_for_each_ctrl(i, display) {
ctrl = &display->ctrl[i];
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
/*
* For phy ver 4.0 chipsets, configure DSI controller and
* DSI PHY to force clk lane to HS mode always whereas
* for other phy ver chipsets, configure DSI controller only.
*/
if (ctrl->phy->hw.ops.set_continuous_clk) {
dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
dsi_phy_set_continuous_clk(ctrl->phy, enable);
} else {
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
}
}
}