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| Filename | Latest commit message | Latest commit date |
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For phy ver 4.0 chipsets, configure DSI controller and DSI PHY to force clk lane to HS mode always. This change was missed while propagating from 4.19 to 5.4. Change-Id: I60370034f7b9ed5d036d9d22f0807250afbcbcd5 Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org> |
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