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Merge 9a4b400adb on remote branch

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Change-Id: I9734696c605cb950ce16d9b1dd59bc2bbbcc2fc1
This commit is contained in:
Linux Build Service Account 2021-05-23 12:52:37 -07:00
commit ef4163147f
30 changed files with 34453 additions and 180 deletions
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5
config/dataipa_gsi_V1.h
View file

@ -1,9 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#define CONFIG_GSI 1
#define CONFIG_RMNET_IPA3 1
#define CONFIG_RNDIS_IPA 1
#define CONFIG_IPA_WDI_UNIFIED_API 1
#define CONFIG_IPA3_REGDUMP 1
#define CONFIG_IPA3_REGDUMP_IPA_4_1 1
#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0

2
config/dataipa_gsi_V1_GKI.conf
View file

@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=m
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=m
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_4_1=y

2
config/dataipa_gsi_V1_QGKI.conf
View file

@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=y
export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=y
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_4_1=y

3
drivers/platform/msm/Makefile
View file

@ -57,6 +57,9 @@ ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m))
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.5
endif
ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_1),y m))
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.1
endif
obj-$(CONFIG_GSI) += gsi/
obj-$(CONFIG_IPA3) += ipa/

141
drivers/platform/msm/gsi/gsi.c
View file

@ -38,6 +38,14 @@
#define GSI_STTS_REG_BITS 32
#define GSI_INST_RAM_FW_VER_OFFSET (0)
#define GSI_INST_RAM_FW_VER_HW_MASK (0xFC00)
#define GSI_INST_RAM_FW_VER_HW_SHIFT (10)
#define GSI_INST_RAM_FW_VER_FLAVOR_MASK (0x380)
#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT (7)
#define GSI_INST_RAM_FW_VER_FW_MASK (0x7f)
#define GSI_INST_RAM_FW_VER_FW_SHIFT (0)
#ifndef CONFIG_DEBUG_FS
void gsi_debugfs_init(void)
{
@ -1820,6 +1828,7 @@ int gsi_alloc_evt_ring(struct gsi_evt_ring_props *props, unsigned long dev_hdl,
((op << GSI_EE_n_EV_CH_CMD_OPCODE_SHFT) &
GSI_EE_n_EV_CH_CMD_OPCODE_BMSK));
ee = gsi_ctx->per.ee;
GSIDBG("Sending alloc evt command for %lu\n", evt_id);
gsi_writel(val, gsi_ctx->base +
GSI_EE_n_EV_CH_CMD_OFFS(ee));
res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT);
@ -3035,7 +3044,14 @@ EXPORT_SYMBOL(gsi_query_channel_db_addr);
int gsi_pending_irq_type(void)
{
int ee = gsi_ctx->per.ee;
int ee;
if (!gsi_ctx->per_registered) {
GSIERR("no client registered\n");
return 0;
}
ee = gsi_ctx->per.ee;
return gsi_readl(gsi_ctx->base +
GSI_EE_n_CNTXT_TYPE_IRQ_OFFS(ee));
@ -3636,6 +3652,7 @@ EXPORT_SYMBOL(gsi_query_channel_info);
int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty)
{
struct gsi_chan_ctx *ctx;
struct gsi_evt_ctx *ev_ctx;
spinlock_t *slock;
unsigned long flags;
uint64_t rp;
@ -3671,8 +3688,11 @@ int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty)
spin_lock_irqsave(slock, flags);
if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI && ctx->evtr) {
rp = gsi_readl(gsi_ctx->base +
GSI_EE_n_EV_CH_k_CNTXT_4_OFFS(ctx->evtr->id, ee));
ev_ctx = &gsi_ctx->evtr[ctx->evtr->id];
/* Read the event ring rp from DDR to avoid mismatch */
rp = ev_ctx->props.gsi_read_event_ring_rp(&ev_ctx->props,
ev_ctx->id, ee);
rp |= ctx->evtr->ring.rp & 0xFFFFFFFF00000000;
ctx->evtr->ring.rp = rp;
@ -4474,6 +4494,45 @@ void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset,
}
EXPORT_SYMBOL(gsi_get_inst_ram_offset_and_size);
/*
* Dumping the Debug registers for halt issue debugging.
*/
static void gsi_dump_halt_debug_reg(unsigned int chan_idx, unsigned int ee)
{
uint32_t val;
enum gsi_chan_state curr_state = GSI_CHAN_STATE_NOT_ALLOCATED;
GSIERR("DEBUG_PC_FOR_DEBUG = 0x%x\n", gsi_readl(gsi_ctx->base +
GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS));
GSIERR("GSI_DEBUG_BUSY_REG 0x%x\n",
gsi_readl(gsi_ctx->base + GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS));
GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS = 0x%x\n",
gsi_readl(gsi_ctx->base +
GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(gsi_ctx->per.ee)));
GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS IRQ type = 0x%x\n",
gsi_readl(gsi_ctx->base +
GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(gsi_ctx->per.ee)));
GSIERR("GSI_EE_n_CNTXT_SCRATCH_0_OFFS = 0x%x\n",
gsi_readl(gsi_ctx->base +
GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee)));
if (gsi_ctx->per.ver >= GSI_VER_2_9)
GSIERR("GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS = 0x%x\n",
gsi_readl(gsi_ctx->base +
GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(chan_idx, ee)));
val = gsi_readl(gsi_ctx->base +
GSI_EE_n_GSI_CH_k_CNTXT_0_OFFS(chan_idx, ee));
curr_state = (val &
GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK) >>
GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT;
GSIERR("Q6 channel [%d] state = %d\n", chan_idx, curr_state);
}
int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code)
{
enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_HALT_CHANNEL;
@ -4528,8 +4587,17 @@ int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code)
}
if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) {
GSIERR("No response received\n");
res = -GSI_STATUS_ERROR;
goto free_lock;
gsi_dump_halt_debug_reg(chan_idx, ee);
usleep_range(GSI_RESET_WA_MIN_SLEEP, GSI_RESET_WA_MAX_SLEEP);
GSIERR("Reading after usleep scratch 0 reg\n");
gsi_ctx->scratch.word0.val = gsi_readl(gsi_ctx->base +
GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee));
if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) {
GSIERR("No response received second attempt\n");
gsi_dump_halt_debug_reg(chan_idx, ee);
res = -GSI_STATUS_ERROR;
goto free_lock;
}
}
res = GSI_STATUS_SUCCESS;
@ -5051,6 +5119,69 @@ static union __packed gsi_channel_scratch __gsi_update_mhi_channel_scratch(
return scr;
}
/**
* gsi_get_hw_profiling_stats() - Query GSI HW profiling stats
* @stats: [out] stats blob from client populated by driver
*
* Returns: 0 on success, negative on failure
*
*/
int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats)
{
if (stats == NULL) {
GSIERR("bad parms NULL stats == NULL\n");
return -EINVAL;
}
stats->bp_cnt = (u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS) +
((u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS) << 32);
stats->bp_and_pending_cnt = (u64)gsi_readl( gsi_ctx->base +
GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS) +
((u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS)
<< 32);
stats->mcs_busy_cnt = (u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS) +
((u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS) << 32);
stats->mcs_idle_cnt = (u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS) +
((u64)gsi_readl(gsi_ctx->base +
GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS) << 32);
return 0;
}
/**
* gsi_get_fw_version() - Query GSI FW version
* @ver: [out] ver blob from client populated by driver
*
* Returns: 0 on success, negative on failure
*
*/
int gsi_get_fw_version(struct gsi_fw_version *ver)
{
u32 raw = 0;
if (ver == NULL) {
GSIERR("bad parms: ver == NULL\n");
return -EINVAL;
}
raw = gsi_readl(gsi_ctx->base +
GSI_V2_5_GSI_INST_RAM_n_OFFS(GSI_INST_RAM_FW_VER_OFFSET));
ver->hw = (raw & GSI_INST_RAM_FW_VER_HW_MASK) >>
GSI_INST_RAM_FW_VER_HW_SHIFT;
ver->flavor = (raw & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >>
GSI_INST_RAM_FW_VER_FLAVOR_SHIFT;
ver->fw = (raw & GSI_INST_RAM_FW_VER_FW_MASK) >>
GSI_INST_RAM_FW_VER_FW_SHIFT;
return 0;
}
static int msm_gsi_probe(struct platform_device *pdev)
{

45
drivers/platform/msm/gsi/gsi.h
View file

@ -1412,6 +1412,32 @@ enum gsi_generic_ee_cmd_return_code {
GSI_GEN_EE_CMD_RETURN_CODE_OUT_OF_RESOURCES = 0x7,
};
/**
* struct gsi_hw_profiling_data - GSI profiling data
* @bp_cnt_lsb: Back Pressure occurences count
* @bp_and_pending_cnt_lsb: Back Pressure with pending back pressure count
* @mcs_busy_cnt_lsb: Cycle count for MCS busy
* @mcs_idle_cnt_lsb: Cycle count for MCS idle
*/
struct gsi_hw_profiling_data {
u64 bp_cnt;
u64 bp_and_pending_cnt;
u64 mcs_busy_cnt;
u64 mcs_idle_cnt;
};
/**
* struct gsi_fw_version - GSI fw version data
* @hw: HW version
* @flavor: Flavor identifier
* @fw: FW version
*/
struct gsi_fw_version {
u32 hw;
u32 flavor;
u32 fw;
};
enum gsi_generic_ee_cmd_query_retun_val {
GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_PRIMARY = 0,
GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_SECONDARY = 1,
@ -2127,6 +2153,25 @@ int gsi_alloc_channel_ee(unsigned int chan_idx, unsigned int ee, int *code);
*/
int gsi_enable_flow_control_ee(unsigned int chan_idx, unsigned int ee,
int *code);
/**
* gsi_get_hw_profiling_stats() - Query GSI HW profiling stats
* @stats: [out] stats blob from client populated by driver
*
* Returns: 0 on success, negative on failure
*
*/
int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats);
/**
* gsi_get_fw_version() - Query GSI FW version
* @ver: [out] ver blob from client populated by driver
*
* Returns: 0 on success, negative on failure
*
*/
int gsi_get_fw_version(struct gsi_fw_version *ver);
int gsi_flow_control_ee(unsigned int chan_idx, unsigned int ee,
bool enable, bool prmy_scnd_fc, int *code);
int gsi_query_flow_control_state_ee(unsigned int chan_idx, unsigned int ee,

102
drivers/platform/msm/gsi/gsi_dbg.c
View file

@ -12,6 +12,8 @@
#include "gsi_reg.h"
#include "gsi.h"
#define GSI_MAX_MSG_LEN 4096
#define TERR(fmt, args...) \
pr_err("%s:%d " fmt, __func__, __LINE__, ## args)
#define TDBG(fmt, args...) \
@ -20,7 +22,7 @@
pr_err(fmt, ## args)
static struct dentry *dent;
static char dbg_buff[4096];
static char dbg_buff[GSI_MAX_MSG_LEN];
static void *gsi_ipc_logbuf_low;
static void gsi_wq_print_dp_stats(struct work_struct *work);
@ -662,6 +664,79 @@ static ssize_t gsi_enable_ipc_low(struct file *file,
return count;
}
static ssize_t gsi_read_gsi_hw_profiling_stats(struct file *file,
char __user *buf, size_t count, loff_t *ppos)
{
struct gsi_hw_profiling_data stats;
int nbytes, cnt = 0;
u64 totalCycles = 0, util = 0;
if (gsi_ctx->per.ver < GSI_VER_2_9) {
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"This feature only support on GSI2.9+\n");
cnt += nbytes;
goto done;
}
if (!gsi_get_hw_profiling_stats(&stats)) {
totalCycles = stats.mcs_busy_cnt + stats.mcs_idle_cnt +
stats.bp_and_pending_cnt;
if (totalCycles != 0)
util = (100 * (stats.mcs_busy_cnt + stats.bp_and_pending_cnt)) /
totalCycles;
else
util = 0;
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"bp_count=0x%llx\n"
"bp_and_pending_count=0x%llx\n"
"mcs_busy=0x%llx\n"
"mcs_idle=0x%llx\n"
"total_cycle_count=0x%llx\n"
"utilization_percentage=%llu%%\n",
stats.bp_cnt,
stats.bp_and_pending_cnt,
stats.mcs_busy_cnt,
stats.mcs_idle_cnt,
totalCycles,
util);
cnt += nbytes;
} else {
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"Fail to read GSI HW Profiling stats\n");
cnt += nbytes;
}
done:
return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt);
}
static ssize_t gsi_read_gsi_fw_version(struct file *file,
char __user *buf, size_t count, loff_t *ppos)
{
struct gsi_fw_version ver;
int nbytes, cnt = 0;
if (gsi_ctx->per.ver < GSI_VER_2_9) {
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"This feature only support on GSI2.9+\n");
cnt += nbytes;
goto done;
}
if (!gsi_get_fw_version(&ver)) {
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"hw=%d\nflavor=%d\nfw=%d\n",
ver.hw,
ver.flavor,
ver.fw);
cnt += nbytes;
} else {
nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN,
"Fail to read GSI FW version\n");
cnt += nbytes;
}
done:
return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt);
}
static const struct file_operations gsi_ev_dump_ops = {
.write = gsi_dump_evt,
};
@ -694,10 +769,19 @@ static const struct file_operations gsi_ipc_low_ops = {
.write = gsi_enable_ipc_low,
};
static const struct file_operations gsi_hw_profiling_ops = {
.read = gsi_read_gsi_hw_profiling_stats,
};
static const struct file_operations gsi_ver_ops = {
.read = gsi_read_gsi_fw_version,
};
void gsi_debugfs_init(void)
{
static struct dentry *dfile;
const mode_t write_only_mode = 0220;
const mode_t read_only_mode = 0440;
dent = debugfs_create_dir("gsi", 0);
if (IS_ERR(dent)) {
@ -761,8 +845,22 @@ void gsi_debugfs_init(void)
goto fail;
}
dfile = debugfs_create_file("gsi_hw_profiling_stats", read_only_mode,
dent, 0, &gsi_hw_profiling_ops);
if (!dfile || IS_ERR(dfile)) {
TERR("could not create gsi_hw_profiling_stats\n");
goto fail;
}
dfile = debugfs_create_file("gsi_fw_version", read_only_mode, dent, 0,
&gsi_ver_ops);
if (!dfile || IS_ERR(dfile)) {
TERR("could not create gsi_fw_version\n");
goto fail;
}
return;
fail:
debugfs_remove_recursive(dent);
}

50
drivers/platform/msm/gsi/gsi_reg_v1.h
View file

@ -1242,4 +1242,54 @@
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5
#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001048)
#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001010)
#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k))
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x0000185c)
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001860)
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001864)
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001868)
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x0000186c)
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001870)
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001874)
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001878)
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0
#endif /* __GSI_REG_V1_H__ */

49
drivers/platform/msm/gsi/gsi_reg_v2.h
View file

@ -1212,4 +1212,53 @@
#define GSI_V2_5_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f
#define GSI_V2_5_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x0000185c)
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001860)
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001864)
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001868)
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x0000186c)
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001870)
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001874)
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_SHFT 0x0
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001878)
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0
#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001048)
#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \
(GSI_GSI_REG_BASE_OFFS + 0x00001010)
#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \
(GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k))
#endif /* __GSI_REG_V2_H__ */

2346
drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h Normal file
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drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h Normal file
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/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#if !defined(_GSI_HWIO_DEF_H_)
#define _GSI_HWIO_DEF_H_
/* *****************************************************************************
*
* HWIO register definitions
*
* *****************************************************************************
*/
struct gsi_hwio_def_gsi_cfg_s {
u32 gsi_enable : 1;
u32 mcs_enable : 1;
u32 double_mcs_clk_freq : 1;
u32 uc_is_mcs : 1;
u32 gsi_pwr_clps : 1;
u32 bp_mtrix_disable : 1;
u32 reserved0 : 26;
};
union gsi_hwio_def_gsi_cfg_u {
struct gsi_hwio_def_gsi_cfg_s def;
u32 value;
};
struct gsi_hwio_def_gsi_ree_cfg_s {
u32 move_to_esc_clr_mode_trsh : 1;
u32 reserved0 : 7;
u32 max_burst_size : 8;
u32 reserved1 : 16;
};
union gsi_hwio_def_gsi_ree_cfg_u {
struct gsi_hwio_def_gsi_ree_cfg_s def;
u32 value;
};
struct gsi_hwio_def_gsi_manager_ee_qos_n_s {
u32 ee_prio : 2;
u32 reserved0 : 6;
u32 max_ch_alloc : 5;
u32 reserved1 : 3;
u32 max_ev_alloc : 5;
u32 reserved2 : 11;
};
union gsi_hwio_def_gsi_manager_ee_qos_n_u {
struct gsi_hwio_def_gsi_manager_ee_qos_n_s def;
u32 value;
};
struct gsi_hwio_def_gsi_shram_n_s {
u32 shram : 32;
};
union gsi_hwio_def_gsi_shram_n_u {
struct gsi_hwio_def_gsi_shram_n_s def;
u32 value;
};
struct gsi_hwio_def_gsi_test_bus_sel_s {
u32 gsi_testbus_sel : 8;
u32 reserved0 : 8;
u32 gsi_hw_events_sel : 4;
u32 reserved1 : 12;
};
union gsi_hwio_def_gsi_test_bus_sel_u {
struct gsi_hwio_def_gsi_test_bus_sel_s def;
u32 value;
};
struct gsi_hwio_def_gsi_test_bus_reg_s {
u32 gsi_testbus_reg : 32;
};
union gsi_hwio_def_gsi_test_bus_reg_u {
struct gsi_hwio_def_gsi_test_bus_reg_s def;
u32 value;
};
struct gsi_hwio_def_gsi_debug_countern_s {
u32 counter_value : 16;
u32 reserved0 : 16;
};
union gsi_hwio_def_gsi_debug_countern_u {
struct gsi_hwio_def_gsi_debug_countern_s def;
u32 value;
};
struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s {
u32 addr_20_0 : 21;
u32 write : 1;
u32 tid : 5;
u32 mid : 5;
};
union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u {
struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def;
u32 value;
};
struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s {
u32 rf_reg : 32;
};
union gsi_hwio_def_gsi_debug_sw_rf_n_read_u {
struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def;
u32 value;
};
struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s {
u32 phy_ch : 5;
u32 valid : 1;
u32 reserved0 : 26;
};
union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u {
struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s def;
u32 value;
};
struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s {
u32 phy_ev_ch : 5;
u32 valid : 1;
u32 reserved0 : 26;
};
union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u {
struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s {
u32 chtype_protocol : 3;
u32 chtype_dir : 1;
u32 ee : 4;
u32 chid : 5;
u32 reserved0 : 1;
u32 erindex : 5;
u32 reserved1 : 1;
u32 chstate : 4;
u32 element_size : 8;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s {
u32 r_length : 16;
u32 reserved0 : 16;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s {
u32 r_base_addr_lsbs : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s {
u32 r_base_addr_msbs : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s {
u32 read_ptr_lsb : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s {
u32 read_ptr_msb : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s {
u32 write_ptr_lsb : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s {
u32 write_ptr_msb : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s {
u32 read_ptr : 16;
u32 reserved0 : 16;
};
union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s {
u32 re_intr_db : 16;
u32 reserved0 : 16;
};
union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s {
u32 wrr_weight : 4;
u32 reserved0 : 4;
u32 max_prefetch : 1;
u32 use_db_eng : 1;
u32 use_escape_buf_only : 1;
u32 reserved1 : 21;
};
union gsi_hwio_def_ee_n_gsi_ch_k_qos_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u {
struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s {
u32 chtype : 4;
u32 ee : 4;
u32 evchid : 8;
u32 intype : 1;
u32 reserved0 : 3;
u32 chstate : 4;
u32 element_size : 8;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s {
u32 r_length : 16;
u32 reserved0 : 16;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s {
u32 r_base_addr_lsbs : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s {
u32 r_base_addr_msbs : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s {
u32 read_ptr_lsb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s {
u32 read_ptr_msb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s {
u32 write_ptr_lsb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s {
u32 write_ptr_msb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s {
u32 int_modt : 16;
u32 int_modc : 8;
u32 int_mod_cnt : 8;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s {
u32 intvec : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s {
u32 msi_addr_lsb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s {
u32 msi_addr_msb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s {
u32 rp_update_addr_lsb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s {
u32 rp_update_addr_msb : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u {
struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u {
struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u {
struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_gsi_status_s {
u32 enabled : 1;
u32 reserved0 : 31;
};
union gsi_hwio_def_ee_n_gsi_status_u {
struct gsi_hwio_def_ee_n_gsi_status_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_type_irq_s {
u32 ch_ctrl : 1;
u32 ev_ctrl : 1;
u32 glob_ee : 1;
u32 ieob : 1;
u32 inter_ee_ch_ctrl : 1;
u32 inter_ee_ev_ctrl : 1;
u32 general : 1;
u32 reserved0 : 25;
};
union gsi_hwio_def_ee_n_cntxt_type_irq_u {
struct gsi_hwio_def_ee_n_cntxt_type_irq_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s {
u32 ch_ctrl : 1;
u32 ev_ctrl : 1;
u32 glob_ee : 1;
u32 ieob : 1;
u32 inter_ee_ch_ctrl : 1;
u32 inter_ee_ev_ctrl : 1;
u32 general : 1;
u32 reserved0 : 25;
};
union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u {
struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s {
u32 gsi_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u {
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s {
u32 ev_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u {
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s {
u32 gsi_ch_bit_map_msk : 17;
u32 reserved0 : 15;
};
union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u {
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s {
u32 ev_ch_bit_map_msk : 12;
u32 reserved0 : 20;
};
union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u {
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s {
u32 gsi_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u {
struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s {
u32 ev_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u {
struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s {
u32 ev_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u {
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s {
u32 ev_ch_bit_map_msk : 12;
u32 reserved0 : 20;
};
union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u {
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s {
u32 ev_ch_bit_map : 32;
};
union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u {
struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s {
u32 error_int : 1;
u32 gp_int1 : 1;
u32 gp_int2 : 1;
u32 gp_int3 : 1;
u32 reserved0 : 28;
};
union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u {
struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s {
u32 gsi_break_point : 1;
u32 gsi_bus_error : 1;
u32 gsi_cmd_fifo_ovrflow : 1;
u32 gsi_mcs_stack_ovrflow : 1;
u32 reserved0 : 28;
};
union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u {
struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_intset_s {
u32 intype : 1;
u32 reserved0 : 31;
};
union gsi_hwio_def_ee_n_cntxt_intset_u {
struct gsi_hwio_def_ee_n_cntxt_intset_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s {
u32 msi_addr_lsb : 32;
};
union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u {
struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s {
u32 msi_addr_msb : 32;
};
union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u {
struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_error_log_s {
u32 error_log : 32;
};
union gsi_hwio_def_ee_n_error_log_u {
struct gsi_hwio_def_ee_n_error_log_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_error_log_clr_s {
u32 error_log_clr : 32;
};
union gsi_hwio_def_ee_n_error_log_clr_u {
struct gsi_hwio_def_ee_n_error_log_clr_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_scratch_0_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_cntxt_scratch_0_u {
struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def;
u32 value;
};
struct gsi_hwio_def_ee_n_cntxt_scratch_1_s {
u32 scratch : 32;
};
union gsi_hwio_def_ee_n_cntxt_scratch_1_u {
struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def;
u32 value;
};
#endif

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/*
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 and only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#if !defined(_IPA_ACCESS_CONTROL_H_)
#define _IPA_ACCESS_CONTROL_H_
#include "ipa_reg_dump.h"
/*
* The following is target specific.
*/
static struct reg_mem_access_map_t mem_access_map[] = {
/*------------------------------------------------------------*/
/* Range Use when Use when */
/* Begin End SD_ENABLED SD_DISABLED */
/*------------------------------------------------------------*/
{ 0x04000, 0x05000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x07000, 0x0f000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x05000, 0x07000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } },
{ 0x0f000, 0x10000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x20000, 0x24000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x24000, 0x28000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x28000, 0x2c000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x10000, 0x11000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x11000, 0x12000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x12000, 0x13000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x43000, 0x44000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x44000, 0x45000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x45000, 0x47000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x40000, 0x42000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x42000, 0x43000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } },
{ 0x47000, 0x4a000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x4a000, 0x5a000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x5a000, 0x5c000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x5e000, 0x60000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x60000, 0x70000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x70000, 0x72000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x72000, 0x80000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
};
#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */

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drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h Normal file
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/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#if !defined(_IPA_GCC_HWIO_DEF_H_)
#define _IPA_GCC_HWIO_DEF_H_
/* *****************************************************************************
*
* HWIO register definitions
*
* *****************************************************************************
*/
struct ipa_gcc_hwio_def_gcc_ipa_bcr_s {
u32 blk_ares : 1;
u32 reserved0 : 31;
};
union ipa_gcc_hwio_def_gcc_ipa_bcr_u {
struct ipa_gcc_hwio_def_gcc_ipa_bcr_s def;
u32 value;
};
#endif

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/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#if !defined(_IPA_HW_COMMON_EX_H_)
#define _IPA_HW_COMMON_EX_H_
/* VLVL defs are available for 854 */
#define FEATURE_VLVL_DEFS true
/* IPAv4 version flag for Sdx24 */
#define FEATURE_IPA_HW_VERSION_4_0 true
/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */
#define IPA_HW_BAM_IRQ_NUM 440
/* Q6 IRQ number for IPA. Fetched from IPCatalog */
#define IPA_HW_IRQ_NUM 441
/* Total number of different interrupts that can be enabled */
#define IPA_HW_IRQ_CNT_TOTAL 23
/* IPAv4 BCR value */
#define IPA_HW_BCR_REG_VAL 0x00000039
/* IPAv4 spare reg value */
#define IPA_HW_SPARE_1_REG_VAL 0xC0000005
/* Whether to allow setting step mode on IPA when we crash or not */
#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false)
/* GSI MHI related definitions */
#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0
#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1
#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1
#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11
/* IPA ZIP WA related Macros */
#define IPA_HW_DCMP_SRC_PIPE 0x8
#define IPA_HW_DCMP_DEST_PIPE 0x4
#define IPA_HW_ACK_MNGR_MASK 0x1D
#define IPA_HW_DCMP_SRC_GRP 0x5
/* IPA Clock resource name */
#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc"
/* IPA Clock Bus Client name */
#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT"
/* HPS Sequences */
#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7
#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8
#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9
/* DPS Sequences */
#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0
#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1
#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2
/* Src RSRC GRP config */
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x05050404
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0A0A0A0A
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0C0C0C0C
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x0E0E0E0E
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x00000101
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x00000808
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x00000808
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x00000E0E
/* Dest RSRC GRP config */
#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x04040404
#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02
#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020303
#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02000201
#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x00020703
#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x00020703
#define IPA_HW_RSRP_GRP_0 0x0
#define IPA_HW_RSRP_GRP_1 0x1
#define IPA_HW_RSRP_GRP_2 0x2
#define IPA_HW_RSRP_GRP_3 0x3
#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0
#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0
#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1
#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1
#define IPA_HW_SRC_RSRP_TYPE_MAX 0x5
#define IPA_HW_DST_RSRP_TYPE_MAX 0x2
#define GSI_HW_QSB_LOG_MISC_MAX 0x4
/* IPA Clock Bus Client name */
#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT"
/* Is IPA decompression feature enabled */
#define IPA_HW_IS_DECOMPRESSION_ENABLED (1)
/* Whether to allow setting step mode on IPA when we crash or not */
#define IPA_HW_IS_STEP_MODE_ALLOWED (true)
/*
* HW specific clock vote freq values in KHz
* (BIMC/SNOC/PCNOC/IPA/Q6 CPU)
*/
enum ipa_hw_clk_freq_e {
/* BIMC */
IPA_HW_CLK_FREQ_BIMC_PEAK = 518400,
IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200,
IPA_HW_CLK_FREQ_BIMC_NOM = 404200,
IPA_HW_CLK_FREQ_BIMC_SVS = 100000,
/* PCNOC */
IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330,
IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000,
IPA_HW_CLK_FREQ_PCNOC_NOM = 100000,
IPA_HW_CLK_FREQ_PCNOC_SVS = 50000,
/*IPA_HW_CLK_SNOC*/
IPA_HW_CLK_FREQ_SNOC_PEAK = 200000,
IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000,
IPA_HW_CLK_FREQ_SNOC_NOM = 150000,
IPA_HW_CLK_FREQ_SNOC_SVS = 85000,
IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000,
/* IPA */
IPA_HW_CLK_FREQ_IPA_PEAK = 500000,
IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 440000,
IPA_HW_CLK_FREQ_IPA_NOM = 440000,
IPA_HW_CLK_FREQ_IPA_SVS = 250000,
IPA_HW_CLK_FREQ_IPA_SVS_2 = 120000,
/* Q6 CPU */
IPA_HW_CLK_FREQ_Q6_PEAK = 729600,
IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600,
IPA_HW_CLK_FREQ_Q6_NOM = 729600,
IPA_HW_CLK_FREQ_Q6_SVS = 729600,
};
/* Pipe ID of all the IPA pipes */
enum ipa_hw_pipe_id_e {
IPA_HW_PIPE_ID_0,
IPA_HW_PIPE_ID_1,
IPA_HW_PIPE_ID_2,
IPA_HW_PIPE_ID_3,
IPA_HW_PIPE_ID_4,
IPA_HW_PIPE_ID_5,
IPA_HW_PIPE_ID_6,
IPA_HW_PIPE_ID_7,
IPA_HW_PIPE_ID_8,
IPA_HW_PIPE_ID_9,
IPA_HW_PIPE_ID_10,
IPA_HW_PIPE_ID_11,
IPA_HW_PIPE_ID_12,
IPA_HW_PIPE_ID_13,
IPA_HW_PIPE_ID_14,
IPA_HW_PIPE_ID_15,
IPA_HW_PIPE_ID_16,
IPA_HW_PIPE_ID_17,
IPA_HW_PIPE_ID_18,
IPA_HW_PIPE_ID_19,
IPA_HW_PIPE_ID_20,
IPA_HW_PIPE_ID_21,
IPA_HW_PIPE_ID_22,
IPA_HW_PIPE_ID_MAX
};
/* Pipe ID's of System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_pipe_id_e {
/* Pipes used by IPA Q6 driver */
IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_3,
IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4,
IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_13,
IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_14,
IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6,
IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_16,
/* Test Simulator Pipes */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_12,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_10,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_2,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_11,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_5,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_17,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_18,
IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_19,
IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX,
};
enum ipa_hw_q6_pipe_ch_id_e {
/* Channels used by IPA Q6 driver */
IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0,
IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1,
IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 3,
IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 4,
IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_CH_ID = 2,
IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_CH_ID = 5,
/* Test Simulator Channels */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 6,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 8,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 9,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 10,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 11,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 12,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 13,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 14,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 15,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 16,
};
/* System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_pipe_e {
/* DL Pipe IPA->Q6 */
IPA_HW_Q6_DL_PRODUCER_PIPE = 0,
/* UL Pipe IPA->Q6 */
IPA_HW_Q6_UL_PRODUCER_PIPE = 1,
/* DL Pipe Q6->IPA */
IPA_HW_Q6_DL_CONSUMER_PIPE = 2,
/* CTL Pipe Q6->IPA */
IPA_HW_Q6_CTL_CONSUMER_PIPE = 3,
/* Q6 -> IPA, LTE DL Optimized path */
IPA_HW_Q6_LTE_DL_CONSUMER_PIPE = 4,
/* LWA DL(Wifi to Q6) */
IPA_HW_Q6_LWA_DL_PRODUCER_PIPE = 5,
/* Diag status pipe IPA->Q6 */
/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 7,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 8,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 9,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 10,
/* SIM B2B PROD Pipe */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 11,
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 12,
/* End FEATURE_IPA_TEST_PER_SIM */
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 13,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 14,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 15,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 16,
IPA_HW_Q6_PIPE_TOTAL
};
/* System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */
/* DL Pipe IPA->Q6 */
IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0,
/* UL Pipe IPA->Q6 */
IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1,
/* DL Pipe Q6->IPA */
//IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2,
/* CTL Pipe Q6->IPA */
//IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3,
/* Q6 -> IPA, LTE DL Optimized path */
//IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4,
/* LWA DL(Wifi to Q6) */
//IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5,
/* Diag status pipe IPA->Q6 */
//IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6,
/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_1_GSI_EV = 5,
IPA_HW_Q6_SIM_2_GSI_EV = 6,
IPA_HW_Q6_SIM_3_GSI_EV = 7,
IPA_HW_Q6_SIM_4_GSI_EV = 8,
IPA_HW_Q6_PIPE_GSI_EV_TOTAL
};
/*
* All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN
* register and read IRQ_STTS register
*/
enum ipa_hw_irq_e {
IPA_HW_IRQ_GSI_HWP = (1 << 25),
IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24),
IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23),
IPA_HW_IRQ_DCMP_ERR = (1 << 22),
IPA_HW_IRQ_HWP_ERR = (1 << 21),
IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20),
IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19),
IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18),
IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17),
IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16),
IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15),
IPA_HW_IRQ_TX_SUSPEND = (1 << 14),
IPA_HW_IRQ_PROC_ERR = (1 << 13),
IPA_HW_IRQ_STEP_MODE = (1 << 12),
IPA_HW_IRQ_TX_ERR = (1 << 11),
IPA_HW_IRQ_DEAGGR_ERR = (1 << 10),
IPA_HW_IRQ_RX_ERR = (1 << 9),
IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8),
IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7),
IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6),
IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5),
IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4),
IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3),
IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2),
IPA_HW_IRQ_EOT_COAL = (1 << 1),
IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0),
IPA_HW_IRQ_NONE = 0,
IPA_HW_IRQ_ALL = 0xFFFFFFFF
};
/*
* All the IRQ sources supported by the IPA HW. Use this enum to set
* IRQ_SRCS register
*/
enum ipa_hw_irq_srcs_e {
IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0),
IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1),
IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2),
IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3),
IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4),
IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5),
IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6),
IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7),
IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8),
IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9),
IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10),
IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11),
IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12),
IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13),
IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14),
IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15),
IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16),
IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17),
IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18),
IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19),
IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20),
IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21),
IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22),
IPA_HW_IRQ_SRCS_NONE = 0,
IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF,
};
/*
* Total number of channel contexts that need to be saved for APPS
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 15
/*
* Total number of channel contexts that need to be saved for UC
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 5
/*
* Total number of event ring contexts that need to be saved for APPS
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 12
/*
* Total number of event ring contexts that need to be saved for UC
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 4
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
* are not saved by default (only if ipa_cfg.gen.full_reg_trace =
* true) There is no extra endpoints in Stingray
*/
#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
* are always saved
*/
#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES 23
/*
* Macro to set the active flag for all active pipe indexed register
*/
#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE() \
do { \
ipa_reg_save.ipa.pipes[0].active = true; \
ipa_reg_save.ipa.pipes[1].active = true; \
ipa_reg_save.ipa.pipes[2].active = true; \
ipa_reg_save.ipa.pipes[3].active = true; \
ipa_reg_save.ipa.pipes[4].active = true; \
ipa_reg_save.ipa.pipes[5].active = true; \
ipa_reg_save.ipa.pipes[6].active = true; \
ipa_reg_save.ipa.pipes[7].active = true; \
ipa_reg_save.ipa.pipes[8].active = true; \
ipa_reg_save.ipa.pipes[9].active = true; \
ipa_reg_save.ipa.pipes[10].active = true; \
ipa_reg_save.ipa.pipes[11].active = true; \
ipa_reg_save.ipa.pipes[12].active = true; \
ipa_reg_save.ipa.pipes[13].active = true; \
ipa_reg_save.ipa.pipes[14].active = true; \
ipa_reg_save.ipa.pipes[15].active = true; \
ipa_reg_save.ipa.pipes[16].active = true; \
ipa_reg_save.ipa.pipes[17].active = true; \
ipa_reg_save.ipa.pipes[18].active = true; \
ipa_reg_save.ipa.pipes[19].active = true; \
ipa_reg_save.ipa.pipes[20].active = true; \
ipa_reg_save.ipa.pipes[21].active = true; \
ipa_reg_save.ipa.pipes[22].active = true; \
} while (0)
/*
* Macro to define a particular register cfg entry for the remaining
* pipe indexed register. In Stingray case we don't have extra
* endpoints so it is intentially empty
*/
#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \
{ 0, 0 }
/*
* Macro to set the active flag for all active pipe indexed register
* In Stingray case we don't have extra endpoints so it is intentially
* empty
*/
#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \
do { \
} while (0)
#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].var_name }
/*
* Macro to define a particular register cfg entry for all GSI EE
* register
*/
#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }
/*
* Macro to define a particular register cfg entry for all pipe
* indexed register
*/
#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
(u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
(u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 5), \
(u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 6), \
(u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 7), \
(u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 8), \
(u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 9), \
(u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 10), \
(u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 11), \
(u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 12), \
(u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 13), \
(u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 14), \
(u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 15), \
(u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 16), \
(u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 17), \
(u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 18), \
(u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 19), \
(u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 20), \
(u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 21), \
(u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 22), \
(u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name }
#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 8
/*
* Total number of rx splt cmdq's see:
* ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX]
*/
#define IPA_RX_SPLT_CMDQ_MAX 3
#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */

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/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#if !defined(_IPA_PKT_CNTXT_H_)
#define _IPA_PKT_CNTXT_H_
#define IPA_HW_PKT_CTNTX_MAX 0x10
#define IPA_HW_NUM_SAVE_PKT_CTNTX 0x8
#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00
#define IPA_HW_PKT_CTNTX_SIZE (sizeof(ipa_pkt_ctntx_opcode_state_s) + \
sizeof(ipa_pkt_ctntx_u))
/*
* Packet Context States
*/
enum ipa_hw_pkt_cntxt_state_e {
IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1,
IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR,
IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP,
IPA_HW_PKT_CNTXT_STATE_H_DCPH,
IPA_HW_PKT_CNTXT_STATE_PKT_PARSER,
IPA_HW_PKT_CNTXT_STATE_FILTER_NAT,
IPA_HW_PKT_CNTXT_STATE_ROUTER,
IPA_HW_PKT_CNTXT_STATE_HDRI,
IPA_HW_PKT_CNTXT_STATE_UCP,
IPA_HW_PKT_CNTXT_STATE_ENQUEUER,
IPA_HW_PKT_CNTXT_STATE_DFETCHER,
IPA_HW_PKT_CNTXT_STATE_D_DCPH,
IPA_HW_PKT_CNTXT_STATE_DISPATCHER,
IPA_HW_PKT_CNTXT_STATE_TX,
IPA_HW_PKT_CNTXT_STATE_TX_ZLT,
IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR,
IPA_HW_PKT_CNTXT_STATE_DCMP,
};
/*
* Packet Context fields as received from VI/Design
*/
struct ipa_pkt_ctntx_s {
u64 opcode : 8;
u64 state : 5;
u64 not_used_1 : 2;
u64 tx_pkt_dma_done : 1;
u64 exc_deagg : 1;
u64 exc_pkt_version : 1;
u64 exc_pkt_len : 1;
u64 exc_threshold : 1;
u64 exc_sw : 1;
u64 exc_nat : 1;
u64 exc_frag_miss : 1;
u64 filter_bypass : 1;
u64 router_bypass : 1;
u64 nat_bypass : 1;
u64 hdri_bypass : 1;
u64 dcph_bypass : 1;
u64 security_credentials_select : 1;
u64 pkt_2nd_pass : 1;
u64 xlat_bypass : 1;
u64 dcph_valid : 1;
u64 ucp_on : 1;
u64 replication : 1;
u64 src_status_en : 1;
u64 dest_status_en : 1;
u64 frag_status_en : 1;
u64 eot_dest : 1;
u64 eot_notif : 1;
u64 prev_eot_dest : 1;
u64 src_hdr_len : 8;
u64 tx_valid_sectors : 8;
u64 rx_flags : 8;
u64 rx_packet_length : 16;
u64 revised_packet_length : 16;
u64 frag_en : 1;
u64 frag_bypass : 1;
u64 frag_process : 1;
u64 notif_pipe : 5;
u64 src_id : 8;
u64 tx_pkt_transferred : 1;
u64 src_pipe : 5;
u64 dest_pipe : 5;
u64 frag_pipe : 5;
u64 ihl_offset : 8;
u64 protocol : 8;
u64 tos : 8;
u64 id : 16;
u64 v6_reserved : 4;
u64 ff : 1;
u64 mf : 1;
u64 pkt_israg : 1;
u64 tx_holb_timer_overflow : 1;
u64 tx_holb_timer_running : 1;
u64 trnseq_0 : 3;
u64 trnseq_1 : 3;
u64 trnseq_2 : 3;
u64 trnseq_3 : 3;
u64 trnseq_4 : 3;
u64 trnseq_ex_length : 8;
u64 trnseq_4_length : 8;
u64 trnseq_4_offset : 8;
u64 dps_tx_pop_cnt : 2;
u64 dps_tx_push_cnt : 2;
u64 vol_ic_dcph_cfg : 1;
u64 vol_ic_tag_stts : 1;
u64 vol_ic_pxkt_init_e : 1;
u64 vol_ic_pkt_init : 1;
u64 tx_holb_counter : 32;
u64 trnseq_0_length : 8;
u64 trnseq_0_offset : 8;
u64 trnseq_1_length : 8;
u64 trnseq_1_offset : 8;
u64 trnseq_2_length : 8;
u64 trnseq_2_offset : 8;
u64 trnseq_3_length : 8;
u64 trnseq_3_offset : 8;
u64 dmar_valid_length : 16;
u64 dcph_valid_length : 16;
u64 frag_hdr_offset : 9;
u64 ip_payload_offset : 9;
u64 frag_rule : 4;
u64 frag_table : 1;
u64 frag_hit : 1;
u64 data_cmdq_ptr : 8;
u64 filter_result : 6;
u64 router_result : 6;
u64 nat_result : 6;
u64 hdri_result : 6;
u64 dcph_result : 6;
u64 dcph_result_valid : 1;
u32 not_used_2 : 4;
u64 tx_pkt_suspended : 1;
u64 tx_pkt_dropped : 1;
u32 not_used_3 : 3;
u64 metadata_valid : 1;
u64 metadata_type : 4;
u64 ul_cs_start_diff : 9;
u64 cs_disable_trlr_vld_bit : 1;
u64 cs_required : 1;
u64 dest_hdr_len : 8;
u64 fr_l : 1;
u64 fl_h : 1;
u64 fr_g : 1;
u64 fr_ret : 1;
u64 fr_rule_id : 10;
u64 rt_l : 1;
u64 rt_h : 1;
u64 rtng_tbl_index : 5;
u64 rt_match : 1;
u64 rt_rule_id : 10;
u64 nat_tbl_index : 13;
u64 nat_type : 2;
u64 hdr_l : 1;
u64 header_offset : 10;
u64 not_used_4 : 1;
u64 filter_result_valid : 1;
u64 router_result_valid : 1;
u64 nat_result_valid : 1;
u64 hdri_result_valid : 1;
u64 not_used_5 : 1;
u64 stream_id : 8;
u64 not_used_6 : 6;
u64 dcph_context_index : 2;
u64 dcph_cfg_size : 16;
u64 dcph_cfg_count : 32;
u64 tag_info : 48;
u64 ucp_cmd_id : 16;
u64 metadata : 32;
u64 ucp_cmd_params : 32;
u64 nat_ip_address : 32;
u64 nat_ip_cs_diff : 16;
u64 frag_dest_pipe : 5;
u64 frag_nat_type : 2;
u64 fragr_ret : 1;
u64 frag_protocol : 8;
u64 src_ip_address : 32;
u64 dest_ip_address : 32;
u64 not_used_7 : 37;
u64 frag_hdr_l : 1;
u64 frag_header_offset : 10;
u64 frag_id : 16;
} __packed;
#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */

103
drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*/
#if !defined(_IPA_HW_COMMON_EX_H_)
#define _IPA_HW_COMMON_EX_H_
@ -505,6 +505,107 @@ enum ipa_hw_irq_srcs_e {
#define IPA_GSI_ADDR 0x00006000
#define IPA_GSI_SIZE round_up(5376, sizeof(u32))
#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\
var_name }
/*
* Macro to define a particular register cfg entry for all GSI EE
* register
*/
#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }
/*
* Macro to define a particular register cfg entry for all pipe
* indexed register

58
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*/
#include "ipa_reg_dump.h"
#include "ipa_access_control.h"
@ -52,12 +52,18 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER,
ipa.gen,
ipa_state_dfetcher),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0,
ipa.gen,
ipa_state_fetcher_mask_0),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1,
ipa.gen,
ipa_state_fetcher_mask_1),
#else
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK,
ipa.gen,
ipa_state_fetcher_mask),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS,
ipa.gen,
ipa_state_gsi_aos),
@ -115,9 +121,6 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR,
ipa.gen,
ipa_log_buf_hw_cmd_ram_ptr),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO,
ipa.gen,
ipa_state_dpl_fifo),
GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION,
ipa.gen,
ipa_comp_hw_version),
@ -172,12 +175,26 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG,
ipa.gen,
ipa_rsrc_grp_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE,
ipa.gen,
ipa_pipeline_disable),
GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG,
ipa.gen,
ipa_comp_cfg),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1)
GEN_SRC_DST_ADDR_MAP(IPA_GSI_CONF,
ipa.gen,
ipa_gsi_conf),
GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER,
ipa.gen,
ipa_tag_timer),
GEN_SRC_DST_ADDR_MAP(IPA_BCR,
ipa.gen,
ipa_bcr),
#else
GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO,
ipa.gen,
ipa_state_dpl_fifo),
GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE,
ipa.gen,
ipa_pipeline_disable),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR,
ipa.gen,
ipa_state_nlo_aggr),
@ -213,12 +230,13 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_nlo_vp_qbap_open),
/* Debug Registers */
GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA,
ipa.dbg,
ipa_debug_data),
GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_BREAKPOINTS,
ipa.dbg,
ipa_step_mode_breakpoints),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA,
ipa.dbg,
ipa_debug_data),
GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS,
ipa.dbg,
ipa_step_mode_status),
@ -352,33 +370,38 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_src_rsrc_grp_01_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n,
ipa_src_rsrc_grp_23_rsrc_type_n),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n,
ipa_src_rsrc_grp_45_rsrc_type_n),
#endif
/* Destination Resource Group Config Registers */
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
ipa_dst_rsrc_grp_01_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,
ipa_dst_rsrc_grp_23_rsrc_type_n),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,
ipa_dst_rsrc_grp_45_rsrc_type_n),
#endif
/* Source Resource Group Count Registers */
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
ipa_src_rsrc_grp_0123_rsrc_type_cnt_n),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
ipa_src_rsrc_grp_4567_rsrc_type_cnt_n),
#endif
/* Destination Resource Group Count Registers */
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n,
ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n),
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(
IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n,
ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n),
#endif
/*
* =====================================================================
* GSI register definitions begin here...
@ -968,6 +991,7 @@ void ipa_save_registers(void)
}
}
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
if (ipa3_ctx->do_ram_collection_on_crash) {
for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_iu_ptr[i] =
@ -1000,7 +1024,7 @@ void ipa_save_registers(void)
IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr);
IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr);
}
#endif
ipa_reg_save_anomaly_check();
IPAERR("Completed\n");
@ -1493,13 +1517,15 @@ int ipa_reg_save_init(u32 value)
i++)
*(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1)
return 0;
#else
ipa_reg_save.ipa.ipa_gsi_ptr = NULL;
ipa_reg_save.ipa.ipa_seq_ptr = NULL;
ipa_reg_save.ipa.ipa_hram_ptr = NULL;
ipa_reg_save.ipa.ipa_mbox_ptr = NULL;
ipa_reg_save.ipa.ipa_sram_ptr = NULL;
ipa_reg_save.ipa.ipa_iu_ptr = NULL;
if (ipa3_ctx->do_ram_collection_on_crash) {
ipa_reg_save.ipa.ipa_iu_ptr =
alloc_and_init(IPA_IU_SIZE, value);
@ -1543,7 +1569,6 @@ int ipa_reg_save_init(u32 value)
goto alloc_fail2;
}
}
return 0;
alloc_fail2:
@ -1553,6 +1578,7 @@ alloc_fail2:
kfree(ipa_reg_save.ipa.ipa_sram_ptr);
kfree(ipa_reg_save.ipa.ipa_iu_ptr);
iounmap(ipa3_ctx->reg_collection_base);
#endif
alloc_fail1:
return -ENOMEM;
}

157
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
*/
#if !defined(_IPA_REG_DUMP_H_)
#define _IPA_REG_DUMP_H_
@ -247,12 +247,12 @@ struct map_src_dst_addr_s {
* indexed register
*/
#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name })
(u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \
{ GEN_SCALER_REG_OFST(reg_name), \
@ -270,7 +270,7 @@ struct map_src_dst_addr_s {
* group register
*/
#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name }, \
@ -279,24 +279,24 @@ struct map_src_dst_addr_s {
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name })
(u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }
/*
* Macro to define a particular register cfg entry for all resource
* group register
*/
#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name })
(u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }
/*
* Macro to define a particular register cfg entry for all source
* resource group count register
*/
#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name }, \
@ -305,142 +305,41 @@ struct map_src_dst_addr_s {
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name })
(u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }
/*
* Macro to define a particular register cfg entry for all dest
* resource group count register
*/
#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name })
#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \
(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\
var_name })
/*
* Macro to define a particular register cfg entry for all GSI EE
* register
*/
#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \
({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name })
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name })
(u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }
/*
* Macro to define a particular register cfg entry for GSI QSB debug
* registers
*/
#define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0] }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1] }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2] }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] })
(u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] }
#define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \
({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.dbg.var_name[0]}, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.dbg.var_name[1]}, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
(u32 *)&ipa_reg_save.ipa.dbg.var_name[2]}, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.ipa.dbg.var_name[3]})
(u32 *)&ipa_reg_save.ipa.dbg.var_name[3]}
/*
* IPA HW Platform Type
@ -448,6 +347,7 @@ struct map_src_dst_addr_s {
enum ipa_hw_ee_e {
IPA_HW_A7_EE = 0, /* A7's execution environment */
IPA_HW_Q6_EE = 1, /* Q6's execution environment */
IPA_HW_UC_EE = 2, /* UC's execution environment */
IPA_HW_HWP_EE = 3, /* HWP's execution environment */
IPA_HW_EE_MAX, /* Max EE to support */
};
@ -471,10 +371,21 @@ struct ipa_gen_regs_s {
ipa_state_aggr_active;
struct ipa_hwio_def_ipa_state_dfetcher_s
ipa_state_dfetcher;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_state_fetcher_mask_0_s
ipa_state_fetcher_mask_0;
struct ipa_hwio_def_ipa_state_fetcher_mask_1_s
ipa_state_fetcher_mask_1;
#else
struct ipa_hwio_def_ipa_gsi_conf_s
ipa_gsi_conf;
struct ipa_hwio_def_ipa_state_fetcher_mask_s
ipa_state_fetcher_mask;
struct ipa_hwio_def_ipa_tag_timer_s
ipa_tag_timer;
struct ipa_hwio_def_ipa_bcr_s
ipa_bcr;
#endif
struct ipa_hwio_def_ipa_state_gsi_aos_s
ipa_state_gsi_aos;
struct ipa_hwio_def_ipa_state_gsi_if_s
@ -551,6 +462,7 @@ struct ipa_gen_regs_s {
ipa_rsrc_grp_cfg;
struct ipa_hwio_def_ipa_comp_cfg_s
ipa_comp_cfg;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_state_dpl_fifo_s
ipa_state_dpl_fifo;
struct ipa_hwio_def_ipa_pipeline_disable_s
@ -577,6 +489,7 @@ struct ipa_gen_regs_s {
ipa_nlo_vp_dsm_open;
struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s
ipa_nlo_vp_qbap_open;
#endif
};
/*
@ -726,8 +639,10 @@ struct ipa_reg_save_dbg_s {
ipa_debug_data;
struct ipa_hwio_def_ipa_step_mode_status_s
ipa_step_mode_status;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_step_mode_breakpoints_s
ipa_step_mode_breakpoints;
#endif
struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s
ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX];
struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s
@ -854,8 +769,10 @@ struct ipa_reg_save_src_rsrc_grp_s {
ipa_src_rsrc_grp_01_rsrc_type_n;
struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s
ipa_src_rsrc_grp_23_rsrc_type_n;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s
ipa_src_rsrc_grp_45_rsrc_type_n;
#endif
};
/* Source Resource Group IPA register save data struct */
@ -864,24 +781,30 @@ struct ipa_reg_save_dst_rsrc_grp_s {
ipa_dst_rsrc_grp_01_rsrc_type_n;
struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s
ipa_dst_rsrc_grp_23_rsrc_type_n;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s
ipa_dst_rsrc_grp_45_rsrc_type_n;
#endif
};
/* Source Resource Group Count IPA register save data struct */
struct ipa_reg_save_src_rsrc_cnt_s {
struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s
ipa_src_rsrc_grp_0123_rsrc_type_cnt_n;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s
ipa_src_rsrc_grp_4567_rsrc_type_cnt_n;
#endif
};
/* Destination Resource Group Count IPA register save data struct */
struct ipa_reg_save_dst_rsrc_cnt_s {
struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s
ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n;
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s
ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n;
#endif
};
/* GSI General register save data struct */
@ -984,6 +907,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = {
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1,
#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5)
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2,
@ -992,6 +916,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = {
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0,
HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8,
#endif
};
/*

126
drivers/platform/msm/ipa/ipa_v3/ipa.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk.h>
@ -154,6 +154,7 @@ static struct clk *ipa3_clk;
struct ipa3_context *ipa3_ctx = NULL;
void ipa3_plat_drv_shutdown(struct platform_device *pdev_p);
int ipa3_plat_drv_probe(struct platform_device *pdev_p);
int ipa3_pci_drv_probe(
struct pci_dev *pci_dev,
@ -443,6 +444,7 @@ static const struct dev_pm_ops ipa_pm_ops = {
static struct platform_driver ipa_plat_drv = {
.probe = ipa3_plat_drv_probe,
.shutdown = ipa3_plat_drv_shutdown,
.driver = {
.name = DRV_NAME,
.pm = &ipa_pm_ops,
@ -1866,6 +1868,7 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
size_t sz;
int pre_entry;
int hdl;
u32 hw_feature_support = 0;
IPADBG("cmd=%x nr=%d\n", cmd, _IOC_NR(cmd));
@ -3080,7 +3083,24 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
retval = ipa3_app_clk_vote(
(enum ipa_app_clock_vote_type) arg);
break;
case IPA_IOC_GET_HW_FEATURE_SUPPORT:
pyld_sz = sizeof(u32);
/*Add new HW feature support to sent to userspace*/
hw_feature_support |= (ipa3_ctx->is_eth_bridging_supported <<
ETH_BRIDGING_SUPPORT);
param = kmemdup(&hw_feature_support, pyld_sz,
GFP_KERNEL);
if (!param) {
retval = -ENOMEM;
break;
}
if (copy_to_user((void __user *)arg, param, pyld_sz)) {
retval = -EFAULT;
break;
}
break;
default:
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
return -ENOTTY;
@ -6003,6 +6023,7 @@ static int ipa3_panic_notifier(struct notifier_block *this,
unsigned long event, void *ptr)
{
int res;
struct ipa_active_client_logging_info log_info;
ipa3_freeze_clock_vote_and_notify_modem();
@ -6011,7 +6032,12 @@ static int ipa3_panic_notifier(struct notifier_block *this,
if (res)
IPAERR("uC panic handler failed %d\n", res);
if (atomic_read(&ipa3_ctx->ipa_clk_vote)) {
/* Make sure IPA clock voted when collecting the reg dump */
IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PANIC_VOTE");
res = ipa3_inc_client_enable_clks_no_block(&log_info);
if (res) {
IPAERR("IPA clk off not saving the IPA registers\n");
} else {
ipahal_print_all_regs(false);
ipa_save_registers();
ipa_wigig_save_regs();
@ -6524,6 +6550,8 @@ fail_teth_bridge_driver_init:
ipa3_teardown_apps_pipes();
fail_alloc_gsi_channel:
fail_setup_apps_pipes:
ipahal_print_all_regs(false);
ipa_save_registers();
gsi_deregister_device(ipa3_ctx->gsi_dev_hdl, false);
fail_register_device:
ipa3_destroy_flt_tbl_idrs();
@ -7174,6 +7202,9 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
}
ipa3_ctx->ipa_endp_delay_wa = resource_p->ipa_endp_delay_wa;
ipa3_ctx->ipa_endp_delay_wa_v2 = resource_p->ipa_endp_delay_wa_v2;
ipa3_ctx->is_eth_bridging_supported =
resource_p->is_eth_bridging_supported;
ipa3_ctx->is_bw_monitor_supported = resource_p->is_bw_monitor_supported;
WARN(ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_NORMAL,
"Non NORMAL IPA HW mode, is this emulation platform ?");
@ -7552,6 +7583,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
}
}
ipa3_ctx->modem_load_ipa_fw = resource_p->modem_load_ipa_fw;
cdev = &ipa3_ctx->cdev.cdev;
cdev_init(cdev, &ipa3_drv_fops);
cdev->owner = THIS_MODULE;
@ -7922,6 +7955,9 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
ipa_drv_res->manual_fw_load = false;
ipa_drv_res->max_num_smmu_cb = IPA_SMMU_CB_MAX;
ipa_drv_res->ipa_endp_delay_wa_v2 = false;
ipa_drv_res->is_eth_bridging_supported = false;
ipa_drv_res->is_bw_monitor_supported = false;
ipa_drv_res->modem_load_ipa_fw = false;
/* Get IPA HW Version */
result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver",
@ -8021,6 +8057,23 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
ipa_drv_res->ipa_endp_delay_wa_v2
? "True" : "False");
if (of_property_read_bool(pdev->dev.of_node,
"qcom,eth-bridging-not-supported"))
ipa_drv_res->is_eth_bridging_supported = false;
else
ipa_drv_res->is_eth_bridging_supported = true;
IPADBG(": ETH bridging supported = %s\n",
ipa_drv_res->is_eth_bridging_supported
? "True" : "False");
ipa_drv_res->is_bw_monitor_supported =
of_property_read_bool(pdev->dev.of_node,
"qcom,bw-monitor-supported");
IPADBG(": BW Monitor and QUOTA stats supported = %s\n",
ipa_drv_res->is_bw_monitor_supported
? "True" : "False");
ipa_drv_res->ipa_wdi3_over_gsi =
of_property_read_bool(pdev->dev.of_node,
@ -8192,6 +8245,13 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
IPADBG(": gsi wdi db polling = %s\n",
ipa_drv_res->gsi_wdi_db_polling
? "True" : "False");
ipa_drv_res->modem_load_ipa_fw =
of_property_read_bool(pdev->dev.of_node,
"qcom,modem-load-ipa-fw");
IPADBG(": Load IPA_FW by modem = %s\n",
ipa_drv_res->modem_load_ipa_fw
? "True" : "False");
result = of_property_read_string(pdev->dev.of_node,
"qcom,use-gsi-ipa-fw", &ipa_drv_res->gsi_fw_file_name);
if (!result)
@ -8920,6 +8980,27 @@ static int ipa3_attach_to_smmu(void)
return 0;
}
static irqreturn_t ipa_smp2p_modem_fw_load_ready_isr(int irq, void *ctxt)
{
int result;
if (!ipa3_ctx->smp2p_info.disabled) {
result = ipa3_attach_to_smmu();
if (result) {
IPAERR("IPA attach to smmu failed %d\n", result);
goto bail;
}
result = ipa3_post_init(&ipa3_res, ipa3_ctx->cdev.dev);
if (result) {
IPAERR("IPA post init failed %d\n", result);
goto bail;
}
ipa3_ctx->smp2p_info.disabled = true;
}
bail:
return IRQ_HANDLED;
}
static irqreturn_t ipa3_smp2p_modem_clk_query_isr(int irq, void *ctxt)
{
ipa3_freeze_clock_vote_and_notify_modem();
@ -8972,6 +9053,23 @@ static int ipa3_smp2p_probe(struct device *dev)
IPAERR("fail to register smp2p irq=%d\n", irq);
return -ENODEV;
}
if (ipa3_ctx->modem_load_ipa_fw) {
res = irq = of_irq_get_byname(node, "ipa-fw-load-ready");
if (res < 0) {
IPADBG("of_irq_get_byname returned %d\n", irq);
return res;
}
res = devm_request_threaded_irq(dev, irq, NULL,
(irq_handler_t)ipa_smp2p_modem_fw_load_ready_isr,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"ipa_fw_load_ready", dev);
if (res) {
IPAERR("fail to register smp2p irq=%d\n", irq);
return -ENODEV;
}
}
}
return 0;
}
@ -8998,6 +9096,30 @@ static void ipa_smmu_update_fw_loader(void)
}
}
void ipa3_plat_drv_shutdown(struct platform_device *pdev_p)
{
int res;
struct ipa_active_client_logging_info log_info;
pr_debug("ipa: driver shutdown invoked for %s\n",
pdev_p->dev.of_node->name);
if(unlikely(!ipa3_ctx))
{
IPAERR("IPA driver not initialized\n");
return;
}
/* Make sure IPA clock voted when collecting the reg dump */
IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "SHUTDOWN_VOTE");
res = ipa3_inc_client_enable_clks_no_block(&log_info);
if (res) {
IPAERR("IPA clk off not saving the IPA registers\n");
} else {
ipahal_print_all_regs(false);
ipa_save_registers();
}
return;
}
int ipa3_plat_drv_probe(struct platform_device *pdev_p)
{
int result;

7
drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
View file

@ -431,6 +431,12 @@ int ipa3_send(struct ipa3_sys_context *sys,
spin_lock_bh(&sys->spinlock);
if (unlikely(atomic_read(&sys->ep->disconnect_in_progress))) {
IPAERR("Pipe disconnect in progress dropping the packet\n");
spin_unlock_bh(&sys->spinlock);
return -EFAULT;
}
for (i = 0; i < num_desc; i++) {
if (!list_empty(&sys->avail_tx_wrapper_list)) {
tx_pkt = list_first_entry(&sys->avail_tx_wrapper_list,
@ -1445,6 +1451,7 @@ int ipa3_teardown_sys_pipe(u32 clnt_hdl)
if (IPA_CLIENT_IS_PROD(ep->client)) {
do {
spin_lock_bh(&ep->sys->spinlock);
atomic_set(&ep->disconnect_in_progress, 1);
empty = list_empty(&ep->sys->head_desc_list);
spin_unlock_bh(&ep->sys->spinlock);
if (!empty)

11
drivers/platform/msm/ipa/ipa_v3/ipa_i.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _IPA3_I_H_
@ -1704,6 +1704,7 @@ struct ipa3_smp2p_info {
u32 in_base_id;
bool ipa_clk_on;
bool res_sent;
bool disabled;
unsigned int smem_bit;
struct qcom_smem_state *smem_state;
};
@ -1951,6 +1952,8 @@ struct ipa3_app_clock_vote {
* @manual_fw_load: bool,if fw load is done manually
* @max_num_smmu_cb: number of smmu s1 cb supported
* @ipa_config_is_auto: flag to indicate auto config
* @is_eth_bridging_supported: Flag to check eth bridging supported or not
* @is_bw_monitor_supported: Flag to check BW monitor supported or not.
*/
struct ipa3_context {
struct ipa3_char_device_context cdev;
@ -2147,6 +2150,9 @@ struct ipa3_context {
u32 num_smmu_cb_probed;
u32 max_num_smmu_cb;
bool ipa_endp_delay_wa_v2;
bool is_eth_bridging_supported;
bool is_bw_monitor_supported;
bool modem_load_ipa_fw;
};
struct ipa3_plat_drv_res {
@ -2216,6 +2222,9 @@ struct ipa3_plat_drv_res {
bool ipa_config_is_auto;
u32 max_num_smmu_cb;
bool ipa_endp_delay_wa_v2;
bool is_eth_bridging_supported;
bool is_bw_monitor_supported;
bool modem_load_ipa_fw;
};
/**

38
drivers/platform/msm/ipa/ipa_v3/ipa_uc.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
*/
#include "ipa_i.h"
@ -98,6 +98,10 @@ enum ipa3_cpu_2_hw_commands {
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 19),
IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 20),
IPA_CPU_2_HW_CMD_QUOTA_MONITORING_YUPIK =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 21),
IPA_CPU_2_HW_CMD_BW_MONITORING_YUPIK =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 22),
};
/**
@ -1574,6 +1578,7 @@ int ipa3_uc_quota_monitor(uint64_t quota)
struct ipa_mem_buffer cmd;
struct IpaQuotaMonitoring_t *quota_info;
IPADBG("Enter\n");
cmd.size = sizeof(*quota_info);
cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size,
&cmd.phys_base, GFP_KERNEL);
@ -1608,11 +1613,17 @@ int ipa3_uc_quota_monitor(uint64_t quota)
IPA_UC_MON_INTERVAL;
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_QUOTA_MONITORING,
IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
false, 10 * HZ);
if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) {
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_QUOTA_MONITORING,
IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
false, 10 * HZ);
} else {
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_QUOTA_MONITORING_YUPIK, 0,
false, 10 * HZ);
}
if (res) {
IPAERR(" faile to set quota %d, number offset %d\n",
quota_info->params.WdiQM.Quota,
@ -1630,6 +1641,7 @@ free_cmd:
dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
IPADBG("Exit\n");
return res;
}
@ -1638,6 +1650,7 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info)
int i, ind, res = 0;
struct ipa_mem_buffer cmd;
struct IpaBwMonitoring_t *bw_info;
IPADBG("Enter\n");
if (!info)
return -EINVAL;
@ -1712,10 +1725,16 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info)
IPA_ACTIVE_CLIENTS_INC_SIMPLE();
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_BW_MONITORING,
IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
false, 10 * HZ);
if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) {
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_BW_MONITORING,
IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
false, 10 * HZ);
} else {
res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
IPA_CPU_2_HW_CMD_BW_MONITORING_YUPIK, 0,
false, 10 * HZ);
}
if (res) {
IPAERR(" faile to set bw %d level with %d coutners\n",
@ -1728,6 +1747,7 @@ free_cmd:
dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
IPADBG("Exit\n");
return res;
}

16
drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
*/
#include <net/ip.h>
@ -3994,14 +3994,14 @@ static struct ipa3_mem_partition ipa_4_11_mem_part = {
.apps_hdr_proc_ctx_size = 0x200,
.apps_hdr_proc_ctx_size_ddr = 0x0,
.nat_tbl_ofst = 0x17A0,
.nat_tbl_size = 0x800,
.pdn_config_ofst = 0x24A8,
.nat_tbl_size = 0x500,
.pdn_config_ofst = 0x1CA8,
.pdn_config_size = 0x50,
.stats_quota_q6_ofst = 0x2500,
.stats_quota_q6_ofst = 0x1D00,
.stats_quota_q6_size = 0x30,
.stats_quota_ap_ofst = 0x2530,
.stats_quota_ap_ofst = 0x1D30,
.stats_quota_ap_size = 0x48,
.stats_tethering_ofst = 0x2578,
.stats_tethering_ofst = 0x1D78,
.stats_tethering_size = 0x238,
.stats_flt_v4_ofst = 0,
.stats_flt_v4_size = 0,
@ -4011,8 +4011,8 @@ static struct ipa3_mem_partition ipa_4_11_mem_part = {
.stats_rt_v4_size = 0,
.stats_rt_v6_ofst = 0,
.stats_rt_v6_size = 0,
.stats_fnr_ofst = 0x27B0,
.stats_fnr_size = 0x0,
.stats_fnr_ofst = 0x1FB0,
.stats_fnr_size = 0x800,
.stats_drop_ofst = 0x27B0,
.stats_drop_size = 0x20,
.modem_comp_decomp_ofst = 0x0,

7
drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018 - 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved.
*/
#include "ipa_i.h"
@ -849,8 +849,9 @@ int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(ipa_ep_idx_tx));
/* start uC event ring */
if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 &&
ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) {
if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 &&
ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) ||
ipa3_ctx->is_bw_monitor_supported) {
if (ipa3_ctx->uc_ctx.uc_loaded &&
!ipa3_ctx->uc_ctx.uc_event_ring_valid) {
if (ipa3_uc_setup_event_ring()) {

18
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
View file

@ -617,8 +617,9 @@ static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v4_filter_init(
static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dummy(
enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx)
{
IPAHAL_ERR("no construct function for IMM_CMD=%s, IPA ver %d\n",
ipahal_imm_cmd_name_str(cmd), ipahal_ctx->hw_type);
IPAHAL_ERR("no construct function for IMM_CMD=%s IPA ver=%d\n",
ipahal_imm_cmd_name_str(cmd), ipahal_ctx?ipahal_ctx->hw_type:-1);
WARN_ON(1);
return NULL;
}
@ -779,6 +780,11 @@ static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd)
{
u32 opcode;
if (!ipahal_ctx) {
IPAHAL_ERR("Invalid ctx\n");
return -EFAULT;
}
if (cmd >= IPA_IMM_CMD_MAX) {
IPAHAL_ERR("Invalid immediate command imm_cmd=%u\n", cmd);
ipa_assert();
@ -813,8 +819,8 @@ struct ipahal_imm_cmd_pyld *ipahal_construct_imm_cmd(
return NULL;
}
if (cmd >= IPA_IMM_CMD_MAX) {
IPAHAL_ERR("Invalid immediate command %u\n", cmd);
if (!ipahal_ctx || cmd >= IPA_IMM_CMD_MAX) {
IPAHAL_ERR("Invalid ctx/immediate command %u\n", cmd);
return NULL;
}
@ -1196,7 +1202,7 @@ u32 ipahal_pkt_status_get_size(void)
void ipahal_pkt_status_parse(const void *unparsed_status,
struct ipahal_pkt_status *status)
{
if (!unparsed_status || !status) {
if (!ipahal_ctx || !unparsed_status || !status) {
IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n",
unparsed_status, status);
return;
@ -1218,7 +1224,7 @@ void ipahal_pkt_status_parse(const void *unparsed_status,
void ipahal_pkt_status_parse_thin(const void *unparsed_status,
struct ipahal_pkt_status_thin *status)
{
if (!unparsed_status || !status) {
if (!ipahal_ctx || !unparsed_status || !status) {
IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n",
unparsed_status, status);
return;

48
drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
View file

@ -3068,8 +3068,11 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = {
ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode,
-1, 0, 0, 0, 0},
[IPA_HW_v4_0][IPA_QSB_MAX_READS] = {
ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_dummy,
ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads,
0x00000078, 0, 0, 0, 0},
[IPA_HW_v4_0][IPA_QSB_MAX_WRITES] = {
ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes,
0x00000074, 0, 0, 0, 0},
[IPA_HW_v4_0][IPA_FILT_ROUT_HASH_FLUSH] = {
ipareg_construct_dummy, ipareg_parse_dummy,
0x0000014c, 0, 0, 0, 0},
@ -3629,15 +3632,16 @@ void ipahal_print_all_regs(bool print_to_dmesg)
int i, j;
struct ipahal_reg_obj *reg;
IPAHAL_DBG("Printing all registers for ipa_hw_type %d\n",
ipahal_ctx->hw_type);
if ((ipahal_ctx->hw_type < IPA_HW_v4_0) ||
if (!ipahal_ctx || (ipahal_ctx->hw_type < IPA_HW_v4_0) ||
(ipahal_ctx->hw_type >= IPA_HW_MAX)) {
IPAHAL_ERR("invalid IPA HW type (%d)\n", ipahal_ctx->hw_type);
IPAHAL_ERR("invalid IPA HW type (%d)\n",
ipahal_ctx?ipahal_ctx->hw_type:-1);
return;
}
IPAHAL_DBG("Printing all registers for ipa_hw_type %d\n",
ipahal_ctx->hw_type);
for (i = 0; i < IPA_REG_MAX ; i++) {
reg = &(ipahal_reg_objs[ipahal_ctx->hw_type][i]);
@ -3753,6 +3757,11 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n)
{
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return -EINVAL;
}
if (reg >= IPA_REG_MAX) {
IPAHAL_ERR("Invalid register reg=%u\n", reg);
WARN_ON(1);
@ -3780,6 +3789,11 @@ u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n)
{
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return -EINVAL;
}
if (reg >= IPA_REG_MAX) {
IPAHAL_ERR("Invalid register reg=%u\n", reg);
WARN_ON(1);
@ -3813,6 +3827,11 @@ void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val)
{
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return;
}
if (reg >= IPA_REG_MAX) {
IPAHAL_ERR("Invalid register reg=%u\n", reg);
WARN_ON(1);
@ -3847,6 +3866,11 @@ u32 ipahal_read_reg_n_fields(enum ipahal_reg_name reg, u32 n, void *fields)
u32 val = 0;
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return -EINVAL;
}
if (!fields) {
IPAHAL_ERR("Input error fields\n");
WARN_ON(1);
@ -3884,6 +3908,11 @@ void ipahal_write_reg_n_fields(enum ipahal_reg_name reg, u32 n,
u32 val = 0;
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return;
}
if (!fields) {
IPAHAL_ERR("Input error fields=%pK\n", fields);
WARN_ON(1);
@ -3918,6 +3947,11 @@ u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n)
{
u32 offset;
if (!ipahal_ctx) {
IPAHAL_DBG("Invalid ipahal context\n");
return -EINVAL;
}
if (reg >= IPA_REG_MAX) {
IPAHAL_ERR("Invalid register reg=%u\n", reg);
WARN_ON(1);
@ -3967,7 +4001,7 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx,
u32 shft = 0;
u32 bmsk = 0;
if (!valmask) {
if (!ipahal_ctx || !valmask) {
IPAHAL_ERR("Input error\n");
return;
}

7
drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
*/
/*
@ -3290,8 +3290,9 @@ static int rmnet_ipa3_set_data_quota_wifi(struct wan_ioctl_set_data_quota *data)
IPAWANDBG("iface name %s, quota %lu\n",
data->interface_name, (unsigned long) data->quota_mbytes);
if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 &&
ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v4_11) {
if ((ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 &&
ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v4_11) ||
ipa3_ctx->is_bw_monitor_supported) {
IPADBG("use ipa-uc for quota\n");
rc = ipa3_uc_quota_monitor(data->set_quota);
} else {