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Merge "ARM: dts: msm: use 'dma-coherent-hint-cached' for fastrpc nodes"

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This commit is contained in:
qctecmdr 2020-04-01 13:43:11 -07:00 • committed by Gerrit - the friendly Code Review server
commit f0227e9ddd
1 changed files with 19 additions and 19 deletions
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38
qcom/lahaina.dtsi
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@ -1890,7 +1890,7 @@
<&apps_smmu 0x1181 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb2 {
@ -1900,7 +1900,7 @@
<&apps_smmu 0x1182 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb3 {
@ -1910,7 +1910,7 @@
<&apps_smmu 0x1183 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb4 {
@ -1920,7 +1920,7 @@
<&apps_smmu 0x1184 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb5 {
@ -1930,7 +1930,7 @@
<&apps_smmu 0x1185 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb6 {
@ -1940,7 +1940,7 @@
<&apps_smmu 0x1186 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb7 {
@ -1950,7 +1950,7 @@
<&apps_smmu 0x1187 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb8 {
@ -1960,7 +1960,7 @@
<&apps_smmu 0x1188 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb9 {
@ -1972,7 +1972,7 @@
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb10 {
@ -1981,7 +1981,7 @@
iommus = <&apps_smmu 0x1803 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb11 {
@ -1990,7 +1990,7 @@
iommus = <&apps_smmu 0x1804 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb12 {
@ -1999,7 +1999,7 @@
iommus = <&apps_smmu 0x1805 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb13 {
@ -2008,7 +2008,7 @@
iommus = <&apps_smmu 0x0541 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb14 {
@ -2017,7 +2017,7 @@
iommus = <&apps_smmu 0x0542 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb15 {
@ -2027,7 +2027,7 @@
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
shared-cb = <4>;
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb16 {
@ -2037,7 +2037,7 @@
<&apps_smmu 0x216B 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb17 {
@ -2047,7 +2047,7 @@
<&apps_smmu 0x216C 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb18 {
@ -2057,7 +2057,7 @@
<&apps_smmu 0x216D 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb19 {
@ -2067,7 +2067,7 @@
<&apps_smmu 0x216E 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
dma-coherent-hint-cached;
};
};