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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add NPU device tree for sa8155/sa8195
Add NPU device tree to support NPU for sa8155/sa8195 Change-Id: I7f18d761ff40b7d2ed443f321aeab3cc65360e40
This commit is contained in:
Jilai Wang
parent
eedf59582d
commit
f1d39ea45f
7 changed files with 906 additions and 0 deletions
164
bindings/media/msm-npu-pwrlevels.txt
Normal file
164
bindings/media/msm-npu-pwrlevels.txt
Normal file
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|
@ -0,0 +1,164 @@
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Qualcomm Technologies, Inc. NPU powerlevels
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Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines
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a series of clock frequencies. These frequencies are for the corresponding
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clocks in the clocks property of the msm_npu device.
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qcom,npu-pwrlevels bindings:
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Required Properties:
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- #address-cells: Should be set to 1
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- #size-cells: Should be set to 0
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- compatible: Must be qcom,npu-pwrlevels
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- initial-pwrlevel: NPU initial wakeup power level, this is the index of the
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child node.
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qcom,npu-pwrlevel: This is a child node defining power levels.
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qcom,npu-pwrlevels must contain at least one power level node. Each child node
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has the following properties:
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Required Properties:
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- reg: Index of the powerlevel (0 = lowest performance)
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- clk-freq: List of clock frequencies (in Hz) of each clock for the current
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powerlevel. List of clocks and order described in:
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Documentation/devicetree/bindings/media/msm-npu.txt
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Example:
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <4>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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clk-freq = <9600000
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9600000
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||||
19200000
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||||
19200000
|
||||
19200000
|
||||
19200000
|
||||
9600000
|
||||
60000000
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||||
19200000
|
||||
19200000
|
||||
30000000
|
||||
19200000
|
||||
19200000
|
||||
19200000
|
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19200000
|
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19200000
|
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9600000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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clk-freq = <300000000
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300000000
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19200000
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100000000
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19200000
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19200000
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300000000
|
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150000000
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19200000
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19200000
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60000000
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100000000
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100000000
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37500000
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100000000
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19200000
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300000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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clk-freq = <350000000
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350000000
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19200000
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150000000
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19200000
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19200000
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350000000
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200000000
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37500000
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19200000
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120000000
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150000000
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150000000
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75000000
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150000000
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19200000
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350000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@3 {
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reg = <3>;
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clk-freq = <400000000
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400000000
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19200000
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200000000
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19200000
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19200000
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400000000
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300000000
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37500000
|
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19200000
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120000000
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200000000
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200000000
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75000000
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200000000
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19200000
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400000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@4 {
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reg = <4>;
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clk-freq = <600000000
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600000000
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19200000
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300000000
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19200000
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19200000
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600000000
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403000000
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75000000
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19200000
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240000000
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300000000
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300000000
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150000000
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300000000
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19200000
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600000000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@5 {
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reg = <5>;
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clk-freq = <715000000
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715000000
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19200000
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350000000
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19200000
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19200000
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715000000
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533000000
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75000000
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19200000
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240000000
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350000000
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350000000
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150000000
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350000000
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19200000
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715000000
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19200000
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0>;
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};
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};
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228
bindings/media/msm-npu.txt
Normal file
228
bindings/media/msm-npu.txt
Normal file
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@ -0,0 +1,228 @@
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* Qualcomm Technologies, Inc. MSM NPU
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NPU (Neural Network Processing Unit) applies neural network processing
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Required properties:
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- compatible: Must be "qcom,msm-npu"
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- reg: Specify offset and length of the device register sets.
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- reg-names: Names corresponding to the defined register sets.
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- "npu_base": npu base registers
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- interrupts: Specify the npu interrupts.
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- interrupt-names: should specify relevant names to each interrupts
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property defined.
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- cache-slice-names: A set of names that identify the usecase names of a
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client that uses cache slice. These strings are used to look up the
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cache slice entries by name
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- cache-slices: The tuple has phandle to llcc device as the first argument
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and the second argument is the usecase id of the client
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- clocks: clocks required for the device.
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- clock-names: names of clocks required for the device.
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- vdd-supply: Phandle for vdd regulator device node
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- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding
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'reg' domain, e.g. vdd_cx-supply.
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- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off
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during proxy voting/unvoting.
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- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator,
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e.g. qcom,vdd_cx-uV-uA.
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- mboxes: Phandle array for mailbox controllers to be used for IPC
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- mbox-names: names of each mailboxes
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- #cooling-cells: Should be set to 2
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- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements
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(see devbw.txt)
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- qcom,npu-pwrlevels: Container for NPU power levels
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(see msm-npu-pwrlevels.txt)
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Example:
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msm_npu: qcom,msm_npu@9800000 {
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compatible = "qcom,msm-npu";
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status = "ok";
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reg = <0x9800000 0x800000>;
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reg-names = "npu_base";
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interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;
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iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
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cache-slice-names = "npu";
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cache-slices = <&llcc 23>;
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clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,
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<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,
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<&clock_npucc NPU_CC_XO_CLK>,
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<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
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<&clock_npucc NPU_CC_BTO_CORE_CLK>,
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<&clock_npucc NPU_CC_BWMON_CLK>,
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<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,
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<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,
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<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_CLK>,
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<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,
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<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
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<&clock_npucc NPU_CC_NPU_CPC_CLK>,
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<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
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<&clock_npucc NPU_CC_PERF_CNT_CLK>,
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<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
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<&clock_npucc NPU_CC_SLEEP_CLK>;
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clock-names = "cal_dp_clk",
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"cal_dp_clk_src",
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"xo_clk",
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"armwic_core_clk",
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"bto_core_clk",
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"bwmon_clk",
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"cal_dp_cdc_clk",
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"comp_noc_axi_clk",
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"conf_noc_ahb_clk",
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"npu_core_apb_clk",
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"npu_core_atb_clk",
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"npu_core_clk",
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"npu_core_clk_src",
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"npu_core_cti_clk",
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"npu_cpc_clk",
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"npu_cpc_timer_clk",
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"perf_cnt_clk",
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"qtimer_core_clk",
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"sleep_clk";
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vdd-supply = <&npu_core_gdsc>;
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vdd_cx-supply = <&pm8150l_s6_level>;
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qcom,proxy-reg-names ="vdd", "vdd_cx";
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;
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mbox-names = "npu_low", "npu_high";
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#cooling-cells = <2>;
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qcom,npubw-dev = <&npu_npu_ddr_bw>;
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <4>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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clk-freq = <9600000
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9600000
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19200000
|
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19200000
|
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19200000
|
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19200000
|
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9600000
|
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60000000
|
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19200000
|
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19200000
|
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30000000
|
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19200000
|
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19200000
|
||||
19200000
|
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19200000
|
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19200000
|
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9600000
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19200000
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0>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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clk-freq = <300000000
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300000000
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19200000
|
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100000000
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19200000
|
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19200000
|
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300000000
|
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150000000
|
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19200000
|
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19200000
|
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60000000
|
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100000000
|
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100000000
|
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37500000
|
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100000000
|
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19200000
|
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300000000
|
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19200000
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0>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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clk-freq = <350000000
|
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350000000
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19200000
|
||||
150000000
|
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19200000
|
||||
19200000
|
||||
350000000
|
||||
200000000
|
||||
37500000
|
||||
19200000
|
||||
120000000
|
||||
150000000
|
||||
150000000
|
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75000000
|
||||
150000000
|
||||
19200000
|
||||
350000000
|
||||
19200000
|
||||
0>;
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};
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qcom,npu-pwrlevel@3 {
|
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reg = <3>;
|
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clk-freq = <400000000
|
||||
400000000
|
||||
19200000
|
||||
200000000
|
||||
19200000
|
||||
19200000
|
||||
400000000
|
||||
300000000
|
||||
37500000
|
||||
19200000
|
||||
120000000
|
||||
200000000
|
||||
200000000
|
||||
75000000
|
||||
200000000
|
||||
19200000
|
||||
400000000
|
||||
19200000
|
||||
0>;
|
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};
|
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qcom,npu-pwrlevel@4 {
|
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reg = <4>;
|
||||
clk-freq = <600000000
|
||||
600000000
|
||||
19200000
|
||||
300000000
|
||||
19200000
|
||||
19200000
|
||||
600000000
|
||||
403000000
|
||||
75000000
|
||||
19200000
|
||||
240000000
|
||||
300000000
|
||||
300000000
|
||||
150000000
|
||||
300000000
|
||||
19200000
|
||||
600000000
|
||||
19200000
|
||||
0>;
|
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};
|
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qcom,npu-pwrlevel@5 {
|
||||
reg = <5>;
|
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clk-freq = <715000000
|
||||
715000000
|
||||
19200000
|
||||
350000000
|
||||
19200000
|
||||
19200000
|
||||
715000000
|
||||
533000000
|
||||
75000000
|
||||
19200000
|
||||
240000000
|
||||
350000000
|
||||
350000000
|
||||
150000000
|
||||
350000000
|
||||
19200000
|
||||
715000000
|
||||
19200000
|
||||
0>;
|
||||
};
|
||||
};
|
||||
};
|
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|
|
@ -171,3 +171,162 @@
|
|||
iommus = <&apps_smmu 0x2304 0x60>;
|
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};
|
||||
};
|
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|
||||
&msm_npu {
|
||||
iommus = <&apps_smmu 0x1481 0x400>, <&apps_smmu 0x1081 0x400>;
|
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qcom,npu-pwrlevels {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
compatible = "qcom,npu-pwrlevels";
|
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initial-pwrlevel = <5>;
|
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qcom,npu-pwrlevel@0 {
|
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reg = <0>;
|
||||
vreg = <1>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
100000000
|
||||
300000000
|
||||
300000000
|
||||
19200000
|
||||
150000000
|
||||
100000000
|
||||
37500000
|
||||
19200000
|
||||
60000000
|
||||
100000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
300000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
vreg = <2>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
150000000
|
||||
400000000
|
||||
400000000
|
||||
37500000
|
||||
200000000
|
||||
150000000
|
||||
75000000
|
||||
19200000
|
||||
120000000
|
||||
150000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
400000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
vreg = <3>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
200000000
|
||||
487000000
|
||||
487000000
|
||||
37500000
|
||||
300000000
|
||||
200000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
200000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
487000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
vreg = <4>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
300000000
|
||||
652000000
|
||||
652000000
|
||||
75000000
|
||||
403000000
|
||||
300000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
300000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
652000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
vreg = <6>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
400000000
|
||||
811000000
|
||||
811000000
|
||||
75000000
|
||||
533000000
|
||||
400000000
|
||||
150000000
|
||||
19200000
|
||||
300000000
|
||||
400000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
811000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
vreg = <7>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
400000000
|
||||
908000000
|
||||
908000000
|
||||
75000000
|
||||
533000000
|
||||
400000000
|
||||
150000000
|
||||
19200000
|
||||
300000000
|
||||
400000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
908000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2090,6 +2090,7 @@
|
|||
#include "sdmshrike-gpu.dtsi"
|
||||
#include "sa8195-vidc.dtsi"
|
||||
#include "sa8155-audio.dtsi"
|
||||
#include "sm8150-npu.dtsi"
|
||||
|
||||
#include "display/sdmshrike-sde-pll.dtsi"
|
||||
#include "display/sdmshrike-sde.dtsi"
|
||||
|
|
|
|||
192
qcom/sm8150-npu.dtsi
Normal file
192
qcom/sm8150-npu.dtsi
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
&soc {
|
||||
msm_npu: qcom,msm_npu@9800000 {
|
||||
compatible = "qcom,msm-npu";
|
||||
status = "ok"
|
||||
reg = <0x9800000 0x40000>,
|
||||
<0x9900000 0x10000>,
|
||||
<0x9960200 0x600>;
|
||||
reg-names = "tcm", "core", "bwmon";
|
||||
interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";
|
||||
iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
|
||||
clocks = <&aopcc QDSS_CLK>,
|
||||
<&gcc GCC_NPU_AT_CLK>,
|
||||
<&gcc GCC_NPU_TRIG_CLK>,
|
||||
<&npucc NPU_CC_ARMWIC_CORE_CLK>,
|
||||
<&npucc NPU_CC_CAL_DP_CLK>,
|
||||
<&npucc NPU_CC_CAL_DP_CDC_CLK>,
|
||||
<&npucc NPU_CC_CONF_NOC_AHB_CLK>,
|
||||
<&npucc NPU_CC_COMP_NOC_AXI_CLK>,
|
||||
<&npucc NPU_CC_NPU_CORE_CLK>,
|
||||
<&npucc NPU_CC_NPU_CORE_CTI_CLK>,
|
||||
<&npucc NPU_CC_NPU_CORE_APB_CLK>,
|
||||
<&npucc NPU_CC_NPU_CORE_ATB_CLK>,
|
||||
<&npucc NPU_CC_NPU_CPC_CLK>,
|
||||
<&npucc NPU_CC_NPU_CPC_TIMER_CLK>,
|
||||
<&npucc NPU_CC_QTIMER_CORE_CLK>,
|
||||
<&npucc NPU_CC_SLEEP_CLK>,
|
||||
<&npucc NPU_CC_BWMON_CLK>,
|
||||
<&npucc NPU_CC_PERF_CNT_CLK>,
|
||||
<&npucc NPU_CC_BTO_CORE_CLK>,
|
||||
<&npucc NPU_CC_XO_CLK>;
|
||||
clock-names = "qdss_clk",
|
||||
"at_clk",
|
||||
"trig_clk",
|
||||
"armwic_core_clk",
|
||||
"cal_dp_clk",
|
||||
"cal_dp_cdc_clk",
|
||||
"conf_noc_ahb_clk",
|
||||
"comp_noc_axi_clk",
|
||||
"npu_core_clk",
|
||||
"npu_core_cti_clk",
|
||||
"npu_core_apb_clk",
|
||||
"npu_core_atb_clk",
|
||||
"npu_cpc_clk",
|
||||
"npu_cpc_timer_clk",
|
||||
"qtimer_core_clk",
|
||||
"sleep_clk",
|
||||
"bwmon_clk",
|
||||
"perf_cnt_clk",
|
||||
"bto_core_clk",
|
||||
"xo_clk";
|
||||
vdd-supply = <&npu_core_gdsc>;
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
qcom,proxy-reg-names ="vdd", "vdd_cx";
|
||||
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
#cooling-cells = <2>;
|
||||
qcom,npu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,npu-pwrlevels";
|
||||
initial-pwrlevel = <4>;
|
||||
qcom,npu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
vreg = <1>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
100000000
|
||||
300000000
|
||||
300000000
|
||||
19200000
|
||||
150000000
|
||||
100000000
|
||||
37500000
|
||||
19200000
|
||||
60000000
|
||||
100000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
300000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
vreg = <2>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
150000000
|
||||
350000000
|
||||
350000000
|
||||
37500000
|
||||
200000000
|
||||
150000000
|
||||
75000000
|
||||
19200000
|
||||
120000000
|
||||
150000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
350000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
vreg = <3>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
200000000
|
||||
400000000
|
||||
400000000
|
||||
37500000
|
||||
300000000
|
||||
200000000
|
||||
75000000
|
||||
19200000
|
||||
120000000
|
||||
200000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
400000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
vreg = <4>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
300000000
|
||||
600000000
|
||||
600000000
|
||||
75000000
|
||||
403000000
|
||||
300000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
300000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
600000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
vreg = <6>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
350000000
|
||||
715000000
|
||||
715000000
|
||||
75000000
|
||||
533000000
|
||||
350000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
350000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
715000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -560,4 +560,165 @@
|
|||
iommus = <&apps_smmu 0x2304 0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
/* NPU overrides */
|
||||
&msm_npu {
|
||||
iommus = <&apps_smmu 0x1081 0x400>;
|
||||
qcom,npu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,npu-pwrlevels";
|
||||
initial-pwrlevel = <5>;
|
||||
qcom,npu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
vreg = <1>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
100000000
|
||||
300000000
|
||||
300000000
|
||||
19200000
|
||||
150000000
|
||||
100000000
|
||||
37500000
|
||||
19200000
|
||||
60000000
|
||||
100000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
300000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
vreg = <2>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
150000000
|
||||
400000000
|
||||
400000000
|
||||
37500000
|
||||
200000000
|
||||
150000000
|
||||
75000000
|
||||
19200000
|
||||
120000000
|
||||
150000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
400000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
vreg = <3>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
200000000
|
||||
487000000
|
||||
487000000
|
||||
37500000
|
||||
300000000
|
||||
200000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
200000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
487000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
vreg = <4>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
300000000
|
||||
652000000
|
||||
652000000
|
||||
75000000
|
||||
403000000
|
||||
300000000
|
||||
150000000
|
||||
19200000
|
||||
240000000
|
||||
300000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
652000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
vreg = <6>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
400000000
|
||||
811000000
|
||||
811000000
|
||||
75000000
|
||||
533000000
|
||||
400000000
|
||||
150000000
|
||||
19200000
|
||||
300000000
|
||||
400000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
811000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
|
||||
qcom,npu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
vreg = <7>;
|
||||
clk-freq = <0
|
||||
0
|
||||
0
|
||||
400000000
|
||||
908000000
|
||||
908000000
|
||||
75000000
|
||||
533000000
|
||||
400000000
|
||||
150000000
|
||||
19200000
|
||||
300000000
|
||||
400000000
|
||||
19200000
|
||||
19200000
|
||||
0
|
||||
19200000
|
||||
908000000
|
||||
19200000
|
||||
19200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "camera/sm8150-v2-camera.dtsi"
|
||||
|
|
|
|||
|
|
@ -2795,3 +2795,4 @@
|
|||
#include "sm8150-pcie.dtsi"
|
||||
#include "sm8150-usb.dtsi"
|
||||
#include "sm8150-gpu.dtsi"
|
||||
#include "sm8150-npu.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue