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msm: pcie: update suppressible clock info

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Update info for suppressible PCIe clocks on chipsets on msm-5.4
and forward.

Change-Id: Ifcde0fbb607b1937e859993199724e916771bd13
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2020-03-23 17:34:30 -07:00 • committed by Gerrit - the friendly Code Review server
commit f339edaac4
1 changed files with 9 additions and 9 deletions
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18
drivers/pci/controller/pci-msm.c
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@ -864,9 +864,9 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_0_smmu_clk", 0, false, false},
{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},
{NULL, "pcie_0_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, true},
{NULL, "pcie_tbu_clk", 0, false, true},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@ -884,9 +884,9 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_1_smmu_clk", 0, false, false},
{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},
{NULL, "pcie_1_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, true},
{NULL, "pcie_tbu_clk", 0, false, true},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@ -904,9 +904,9 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_2_smmu_clk", 0, false, false},
{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},
{NULL, "pcie_2_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, true},
{NULL, "pcie_tbu_clk", 0, false, true},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},