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Merge "msm: ep-pcie: Correct two CAP reg offsets"
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commit
f716cd752c
2 changed files with 11 additions and 6 deletions
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@ -105,8 +105,8 @@
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#define PCIE20_CAP_LINKCTRLSTATUS 0x80
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#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
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#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0
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#define PCIE20_L1SUB_CAPABILITY 0x154
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#define PCIE20_L1SUB_CONTROL1 0x158
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#define PCIE20_L1SUB_CAPABILITY 0x234
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#define PCIE20_L1SUB_CONTROL1 0x238
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#define PCIE20_BUS_DISCONNECT_STATUS 0x68c
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#define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C
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#define PCIE20_MASK_ACK_N_FTS 0xff00
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@ -657,10 +657,6 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
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PCIE20_LINK_CONTROL2_LINK_STATUS2,
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0xf, dev->link_speed);
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EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",
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dev->rev);
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ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
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EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",
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dev->rev);
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ep_pcie_write_reg_field(dev->tcsr_perst_en,
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@ -1976,6 +1972,11 @@ checkbme:
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dev->rev, retries,
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BME_TIMEOUT_US_MIN * retries / 1000);
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ep_pcie_enumeration_complete(dev);
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EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",
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dev->rev);
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ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
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/* expose BAR to user space to identify modem */
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ep_pcie_bar0_address =
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readl_relaxed(dev->dm_core + PCIE20_BAR0);
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@ -2149,6 +2150,10 @@ static irqreturn_t ep_pcie_handle_bme_irq(int irq, void *data)
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dev->rev);
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ep_pcie_notify_event(dev, EP_PCIE_EVENT_LINKUP);
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}
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EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",
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dev->rev);
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ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
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} else {
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EP_PCIE_DBG(dev,
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"PCIe V%d:BME is still disabled\n", dev->rev);
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